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[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226681 91177308-0d34-0410-b5e6-96231b3b80d8
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Colin LeMahieu
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34288d885e
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62b9c33e13
@ -53,6 +53,10 @@ class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
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: Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
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(MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
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class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
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(MI I32:$Rs, I32:$Rt, imm:$Iu)>;
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class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
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(MI I32:$Rs, I32:$Rt, I32:$Ru)>;
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@ -333,6 +337,23 @@ def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
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def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
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def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
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// Multiply 32x32 and use lower result
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def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
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def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
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def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
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// Subtract and accumulate
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def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
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// Add and accumulate
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def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>;
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def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>;
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def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>;
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def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
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// XOR and XOR with destination
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def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
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//
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// ALU 32 types.
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//
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120
test/CodeGen/Hexagon/intrinsics-mpy-acc.ll
Normal file
120
test/CodeGen/Hexagon/intrinsics-mpy-acc.ll
Normal file
@ -0,0 +1,120 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Verify that the mpy intrinsics with add/subtract are being lowered to the right instruction.
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@c = external global i64
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}#124)
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define void @test1(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.macsip(i32 %conv, i32 %a, i32 124)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.macsip(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}#166)
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define void @test2(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.macsin(i32 %conv, i32 %a, i32 166)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.macsin(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test3(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.maci(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.maci(i32, i32, i32) #1
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@d = external global i32
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#40)
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define void @test7(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.accii(i32 %conv, i32 %a, i32 40)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.accii(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#100)
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define void @test8(i32 %a) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.naccii(i32 %conv, i32 %a, i32 100)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test9(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.acci(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.acci(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}sub(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test10(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.subacc(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32) #1
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; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test11(i32 %a, i32 %b) #0 {
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entry:
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%0 = load i64* @c, align 8
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%conv = trunc i64 %0 to i32
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%1 = tail call i32 @llvm.hexagon.M2.nacci(i32 %conv, i32 %a, i32 %b)
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%conv1 = sext i32 %1 to i64
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store i64 %conv1, i64* @c, align 8
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ret void
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}
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declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32) #1
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