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Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriately
Leaving MFCR has having unmodeled side effects is not enough to prevent unwanted instruction reordering post-RA. We could probably apply a stronger barrier attribute, but there is a better way: Add all (not just the first) CR to be spilled as live-in to the entry block, and add all CRs to the MFCR instruction as implicitly killed. Unfortunately, I don't have a small test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179465 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1122,18 +1122,21 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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*static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
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DebugLoc DL;
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bool CRSpilled = false;
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MachineInstrBuilder CRMIB;
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// CR2 through CR4 are the nonvolatile CR fields.
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bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
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if (CRSpilled && IsCRField)
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continue;
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// Add the callee-saved register as live-in; it's killed at the spill.
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MBB.addLiveIn(Reg);
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if (CRSpilled && IsCRField) {
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CRMIB.addReg(Reg, RegState::ImplicitKill);
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continue;
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}
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// Insert the spill to the stack frame.
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if (IsCRField) {
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CRSpilled = true;
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@ -1143,7 +1146,10 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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// 64-bit: SP+8
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bool is31 = needsFP(*MF);
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unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
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MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR8), PPC::X12));
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CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR8), PPC::X12)
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.addReg(Reg, RegState::ImplicitKill);
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MBB.insert(MI, CRMIB);
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MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW8))
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.addReg(PPC::X12,
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getKillRegState(true))
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@ -1152,7 +1158,10 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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} else {
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// 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
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// the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
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MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12));
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CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
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.addReg(Reg, RegState::ImplicitKill);
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MBB.insert(MI, CRMIB);
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MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
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.addReg(PPC::R12,
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getKillRegState(true)),
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@ -256,11 +256,7 @@ def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
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PPC970_MicroCode, PPC970_Unit_CRU;
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} // neverHasSideEffects = 1
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// MFCR uses all CR registers, but marking that explicitly causes
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// problems because some of them appear to be undefined. Because
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// this form is used only in prologue code, just mark it as having
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// side effects.
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let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in
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let neverHasSideEffects = 1 in
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def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
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"mfcr $rT", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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@ -1618,11 +1618,7 @@ def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
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PPC970_DGroup_First, PPC970_Unit_CRU;
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} // neverHasSideEffects = 1
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// MFCR uses all CR registers, but marking that explicitly causes
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// problems because some of them appear to be undefined. Because
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// this form is used only in prologue code, just mark it as having
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// side effects.
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let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in
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let neverHasSideEffects = 1 in
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def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
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"mfcr $rT", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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