Fix a problem where lib/Target/TargetInstrInfo.h would include and use

a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetInstrInfo.h

@@ -406,7 +406,7 @@ public:
   /// return a new machine instruction.  If an instruction cannot commute, it
   /// can also return null.
   ///
-  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
 
   /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
@@ -504,7 +504,7 @@ public:
   /// instruction. It returns true if the operation was successful.
   virtual
   bool PredicateInstruction(MachineInstr *MI,
-                            const std::vector<MachineOperand> &Pred) const;
+                            const std::vector<MachineOperand> &Pred) const = 0;
 
   /// SubsumesPredicate - Returns true if the first specified predicate
   /// subsumes the second, e.g. GE subsumes GT.
@@ -531,6 +531,21 @@ public:
   }
 };
 
+/// TargetInstrInfoImpl - This is the default implementation of
+/// TargetInstrInfo, which just provides a couple of default implementations
+/// for various methods.  This separated out because it is implemented in
+/// libcodegen, not in libtarget.
+class TargetInstrInfoImpl : public TargetInstrInfo {
+protected:
+  TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
+  : TargetInstrInfo(desc, NumOpcodes) {}
+public:
+  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+  virtual bool PredicateInstruction(MachineInstr *MI,
+                              const std::vector<MachineOperand> &Pred) const;
+  
+};
+
 } // End llvm namespace
 
 #endif

lib/CodeGen/TargetInstrInfoImpl.cpp

@@ -0,0 +1,58 @@
+//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetInstrInfoImpl class, it just provides default
+// implementations of various methods.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
+using namespace llvm;
+
+// commuteInstruction - The default implementation of this method just exchanges
+// operand 1 and 2.
+MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
+  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+         "This only knows how to commute register operands so far");
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(2).getReg();
+  bool Reg1IsKill = MI->getOperand(1).isKill();
+  bool Reg2IsKill = MI->getOperand(2).isKill();
+  MI->getOperand(2).setReg(Reg1);
+  MI->getOperand(1).setReg(Reg2);
+  MI->getOperand(2).setIsKill(Reg1IsKill);
+  MI->getOperand(1).setIsKill(Reg2IsKill);
+  return MI;
+}
+
+bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
+                                               const std::vector<MachineOperand> &Pred) const {
+  bool MadeChange = false;
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if (TID->Flags & M_PREDICABLE) {
+    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isReg()) {
+          MO.setReg(Pred[j].getReg());
+          MadeChange = true;
+        } else if (MO.isImm()) {
+          MO.setImm(Pred[j].getImm());
+          MadeChange = true;
+        } else if (MO.isMBB()) {
+          MO.setMBB(Pred[j].getMBB());
+          MadeChange = true;
+        }
+        ++j;
+      }
+    }
+  }
+  return MadeChange;
+}

lib/Target/ARM/ARMInstrInfo.cpp

@@ -38,7 +38,7 @@ const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
 }
 
 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
-  : TargetInstrInfo(ARMInsts, array_lengthof(ARMInsts)),
+  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
     RI(*this, STI) {
 }
 

lib/Target/ARM/ARMInstrInfo.h

@@ -125,7 +125,7 @@ namespace ARMII {
   };
 }
 
-class ARMInstrInfo : public TargetInstrInfo {
+class ARMInstrInfo : public TargetInstrInfoImpl {
   const ARMRegisterInfo RI;
 public:
   ARMInstrInfo(const ARMSubtarget &STI);

lib/Target/Alpha/AlphaInstrInfo.cpp

@@ -19,7 +19,7 @@
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()
-  : TargetInstrInfo(AlphaInsts, array_lengthof(AlphaInsts)),
+  : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
     RI(*this) { }
 
 

lib/Target/Alpha/AlphaInstrInfo.h

@@ -19,7 +19,7 @@
 
 namespace llvm {
 
-class AlphaInstrInfo : public TargetInstrInfo {
+class AlphaInstrInfo : public TargetInstrInfoImpl {
   const AlphaRegisterInfo RI;
 public:
   AlphaInstrInfo();

lib/Target/CellSPU/SPUInstrInfo.cpp

@@ -21,7 +21,7 @@
 using namespace llvm;
 
 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
-  : TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
+  : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
     TM(tm),
     RI(*TM.getSubtargetImpl(), *this)
 {

lib/Target/CellSPU/SPUInstrInfo.h

@@ -20,8 +20,7 @@
 
 namespace llvm {
   //! Cell SPU instruction information class
-  class SPUInstrInfo : public TargetInstrInfo
-  {
+  class SPUInstrInfo : public TargetInstrInfoImpl {
     SPUTargetMachine &TM;
     const SPURegisterInfo RI;
   public:

lib/Target/IA64/IA64InstrInfo.cpp

@@ -19,7 +19,7 @@
 using namespace llvm;
 
 IA64InstrInfo::IA64InstrInfo()
-  : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
+  : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
     RI(*this) {
 }
 

lib/Target/IA64/IA64InstrInfo.h

@@ -19,7 +19,7 @@
 
 namespace llvm {
 
-class IA64InstrInfo : public TargetInstrInfo {
+class IA64InstrInfo : public TargetInstrInfoImpl {
   const IA64RegisterInfo RI;
 public:
   IA64InstrInfo();

lib/Target/Mips/MipsInstrInfo.cpp

@@ -21,7 +21,7 @@ using namespace llvm;
 
 // TODO: Add the subtarget support on this constructor
 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
-  : TargetInstrInfo(MipsInsts, array_lengthof(MipsInsts)),
+  : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
     TM(tm), RI(*this) {}
 
 static bool isZeroImm(const MachineOperand &op) {

lib/Target/Mips/MipsInstrInfo.h

@@ -42,8 +42,7 @@ namespace Mips {
 
 }
 
-class MipsInstrInfo : public TargetInstrInfo 
-{
+class MipsInstrInfo : public TargetInstrInfoImpl {
   MipsTargetMachine &TM;
   const MipsRegisterInfo RI;
 public:

lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -20,7 +20,7 @@
 using namespace llvm;
 
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
-  : TargetInstrInfo(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
+  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
     RI(*TM.getSubtargetImpl(), *this) {}
 
 /// getPointerRegClass - Return the register class to use to hold pointers.

lib/Target/PowerPC/PPCInstrInfo.h

@@ -61,7 +61,7 @@ enum PPC970_Unit {
 }
   
   
-class PPCInstrInfo : public TargetInstrInfo {
+class PPCInstrInfo : public TargetInstrInfoImpl {
   PPCTargetMachine &TM;
   const PPCRegisterInfo RI;
 public:

lib/Target/Sparc/SparcInstrInfo.cpp

@@ -20,7 +20,7 @@
 using namespace llvm;
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
-  : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)),
+  : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
     RI(ST, *this), Subtarget(ST) {
 }
 

lib/Target/Sparc/SparcInstrInfo.h

@@ -31,7 +31,7 @@ namespace SPII {
   };
 }
 
-class SparcInstrInfo : public TargetInstrInfo {
+class SparcInstrInfo : public TargetInstrInfoImpl {
   const SparcRegisterInfo RI;
   const SparcSubtarget& Subtarget;
 public:

lib/Target/TargetInstrInfo.cpp

@@ -12,7 +12,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Constant.h"
 #include "llvm/DerivedTypes.h"
 using namespace llvm;
@@ -38,47 +37,6 @@ TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
 TargetInstrInfo::~TargetInstrInfo() {
 }
 
-// commuteInstruction - The default implementation of this method just exchanges
-// operand 1 and 2.
-MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
-  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
-         "This only knows how to commute register operands so far");
-  unsigned Reg1 = MI->getOperand(1).getReg();
-  unsigned Reg2 = MI->getOperand(2).getReg();
-  bool Reg1IsKill = MI->getOperand(1).isKill();
-  bool Reg2IsKill = MI->getOperand(2).isKill();
-  MI->getOperand(2).setReg(Reg1);
-  MI->getOperand(1).setReg(Reg2);
-  MI->getOperand(2).setIsKill(Reg1IsKill);
-  MI->getOperand(1).setIsKill(Reg2IsKill);
-  return MI;
-}
-
-bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                const std::vector<MachineOperand> &Pred) const {
-  bool MadeChange = false;
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  if (TID->Flags & M_PREDICABLE) {
-    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
-        MachineOperand &MO = MI->getOperand(i);
-        if (MO.isReg()) {
-          MO.setReg(Pred[j].getReg());
-          MadeChange = true;
-        } else if (MO.isImm()) {
-          MO.setImm(Pred[j].getImm());
-          MadeChange = true;
-        } else if (MO.isMBB()) {
-          MO.setMBB(Pred[j].getMBB());
-          MadeChange = true;
-        }
-        ++j;
-      }
-    }
-  }
-  return MadeChange;
-}
-
 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   if (TID->Flags & M_TERMINATOR_FLAG) {

lib/Target/X86/X86InstrInfo.cpp

@@ -25,7 +25,7 @@
 using namespace llvm;
 
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
-  : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
+  : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
     TM(tm), RI(tm, *this) {
 }
 

lib/Target/X86/X86InstrInfo.h

@@ -222,7 +222,7 @@ namespace X86II {
   };
 }
 
-class X86InstrInfo : public TargetInstrInfo {
+class X86InstrInfo : public TargetInstrInfoImpl {
   X86TargetMachine &TM;
   const X86RegisterInfo RI;
   mutable IndexedMap<const MachineInstr*, VirtReg2IndexFunctor> MachineInstrMap;