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Fix two typos I found in comments.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9806 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2003-11-08 18:12:24 +00:00
parent 3e2959e2a0
commit 641271df3c
2 changed files with 3 additions and 3 deletions
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4
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -760,7 +760,7 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g2 for holding large offsets
// Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
#endif
@ -845,7 +845,7 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g2 for holding large offsets
// Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
#endif

2
lib/Target/SparcV9/SparcV9_Reg.td
View File

@ -32,7 +32,7 @@ let Namespace = "SparcV9" in {
// For fun, specify a register class.
//
// FIXME: the register order should be defined in terms of the prefered
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,