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Provide proper stack offsets for outgoing arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75945 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -38,6 +38,8 @@ using namespace llvm;
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SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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RegInfo = TM.getRegisterInfo();
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// Set up the register classes.
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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@ -190,6 +192,7 @@ SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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SDValue Callee = TheCall->getCallee();
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = Op.getDebugLoc();
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MachineFunction &MF = DAG.getMachineFunction();
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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@ -237,12 +240,16 @@ SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, dl, SystemZ::R15D, getPointerTy());
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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DAG.getIntPtrConstant(VA.getLocMemOffset()));
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StackPtr =
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DAG.getCopyFromReg(Chain, dl,
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(RegInfo->hasFP(MF) ?
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SystemZ::R11D : SystemZ::R15D),
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getPointerTy());
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SDValue PtrOff =
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DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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DAG.getIntPtrConstant(160+VA.getLocMemOffset()));
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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PseudoSourceValue::getStack(),
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@ -16,6 +16,7 @@
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#define LLVM_TARGET_SystemZ_ISELLOWERING_H
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#include "SystemZ.h"
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#include "SystemZRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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@ -61,6 +62,7 @@ namespace llvm {
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private:
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const SystemZSubtarget &Subtarget;
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const SystemZTargetMachine &TM;
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const SystemZRegisterInfo *RegInfo;
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};
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} // namespace llvm
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@ -33,7 +33,7 @@ public:
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
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bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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@ -48,7 +48,7 @@ public:
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virtual const TargetData *getTargetData() const { return &DataLayout;}
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virtual const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
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virtual const TargetRegisterInfo *getRegisterInfo() const {
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virtual const SystemZRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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