6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-24 22:24:54 +00:00
Code Issues Projects Releases Wiki Activity

Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and

Browse Source 
VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.

This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37569 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2007-06-13 15:12:02 +00:00
parent 2046e12f02
commit 6595635175
4 changed files with 96 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@@ -2865,6 +2865,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt";
case ISD::VCONCAT_VECTORS: return "vconcat_vectors";
case ISD::VEXTRACT_SUBVECTOR: return "vextract_subvector";
case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
case ISD::VBUILD_VECTOR: return "vbuild_vector";
case ISD::VECTOR_SHUFFLE: return "vector_shuffle";