6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 18:29:45 +00:00
Code Issues Projects Releases Wiki Activity

[AArch64] Use the correct register class for ORR.

Browse Source 
While fixing up the register classes in the machine combiner in a previous
commit I missed one.

This fixes the last one and adds a test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-11-04 22:20:07 +00:00
parent 2ca0328c3b
commit 6612e3aeda
2 changed files with 19 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -2805,7 +2805,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::GPR32RegClass;
} else {
OrrOpc = AArch64::ORRXri;
OrrRC = &AArch64::GPR64RegClass;
OrrRC = &AArch64::GPR64spRegClass;
BitSize = 64;
ZeroReg = AArch64::XZR;
Opc = AArch64::MADDXrrr;

19
test/CodeGen/AArch64/madd-combiner.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
; Test that we use the correct register class.
define i32 @mul_add_imm(i32 %a, i32 %b) {
@ -18,3 +19,19 @@ define i32 @mul_sub_imm1(i32 %a, i32 %b) {
%2 = sub i32 4, %1
ret i32 %2
}
; bugpoint reduced test case. This only tests that we pass the MI verifier.
define void @mul_add_imm2() {
entry:
br label %for.body
for.body:
br i1 undef, label %for.body, label %for.body8
for.body8:
%0 = mul i64 undef, -3
%mul1971 = add i64 %0, -3
%cmp7 = icmp slt i64 %mul1971, 1390451930000
br i1 %cmp7, label %for.body8, label %for.end20
for.end20:
ret void
}