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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1750,9 +1750,10 @@ class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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// NEON 3 vector register format.
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class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
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dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr, list<dag> pattern>
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class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
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bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr,
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list<dag> pattern>
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: NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
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let Inst{24} = op24;
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let Inst{23} = op23;
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@ -1781,9 +1782,10 @@ class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
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let Inst{5} = Vm{4};
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}
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class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
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dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr, list<dag> pattern>
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class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
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bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr,
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list<dag> pattern>
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: N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
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oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
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@ -1801,9 +1803,10 @@ class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bi
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let Inst{5} = lane;
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}
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class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
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dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr, list<dag> pattern>
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class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
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bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr,
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list<dag> pattern>
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: N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
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oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
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