mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
8194683d5a
commit
67609fd0eb
@ -8419,38 +8419,30 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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// We are handling one of the integer comparisons here. Since SSE only has
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// GT and EQ comparisons for integer, swapping operands and multiple
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// operations may be required for some comparisons.
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unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
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unsigned Opc = 0;
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bool Swap = false, Invert = false, FlipSigns = false;
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switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
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default: break;
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case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
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case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
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case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
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case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
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}
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETNE: Invert = true;
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case ISD::SETEQ: Opc = EQOpc; break;
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case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
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case ISD::SETLT: Swap = true;
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case ISD::SETGT: Opc = GTOpc; break;
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case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
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case ISD::SETGE: Swap = true;
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case ISD::SETLE: Opc = GTOpc; Invert = true; break;
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case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
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case ISD::SETULT: Swap = true;
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case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
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case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
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case ISD::SETUGE: Swap = true;
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case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
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case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
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}
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if (Swap)
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std::swap(Op0, Op1);
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// Check that the operation in question is available (most are plain SSE2,
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// but PCMPGTQ and PCMPEQQ have different requirements).
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if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42())
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if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
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return SDValue();
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if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41())
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if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
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return SDValue();
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// Since SSE has no unsigned integer comparisons, we need to flip the sign
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@ -10108,7 +10100,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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// R s>> 7 === R s< 0
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SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
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/* HasAVX2 */false, DAG, dl);
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return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
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return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
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}
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// R s>> a === ((R u>> a) ^ m) - m
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@ -10152,7 +10144,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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// R s>> 7 === R s< 0
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SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
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true /* HasAVX2 */, DAG, dl);
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return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
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return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
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}
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// R s>> a === ((R u>> a) ^ m) - m
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@ -10198,7 +10190,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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// Turn 'a' into a mask suitable for VSELECT
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SDValue VSelM = DAG.getConstant(0x80, VT);
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SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
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OpVSel = DAG.getNode(X86ISD::PCMPEQB, dl, VT, OpVSel, VSelM);
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OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
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SDValue CM1 = DAG.getConstant(0x0f, VT);
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SDValue CM2 = DAG.getConstant(0x3f, VT);
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@ -10213,7 +10205,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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// a += a
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Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
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OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
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OpVSel = DAG.getNode(X86ISD::PCMPEQB, dl, VT, OpVSel, VSelM);
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OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
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// r = VSELECT(r, psllw(r & (char16)63, 2), a);
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M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
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@ -10225,7 +10217,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
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// a += a
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Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
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OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
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OpVSel = DAG.getNode(X86ISD::PCMPEQB, dl, VT, OpVSel, VSelM);
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OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
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// return VSELECT(r, r+r, a);
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R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
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@ -10945,14 +10937,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VSRAI: return "X86ISD::VSRAI";
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case X86ISD::CMPPD: return "X86ISD::CMPPD";
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case X86ISD::CMPPS: return "X86ISD::CMPPS";
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case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
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case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
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case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
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case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
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case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
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case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
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case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
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case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
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case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
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case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
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case X86ISD::ADD: return "X86ISD::ADD";
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case X86ISD::SUB: return "X86ISD::SUB";
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case X86ISD::ADC: return "X86ISD::ADC";
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@ -233,8 +233,7 @@ namespace llvm {
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CMPPD, CMPPS,
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// PCMP* - Vector integer comparisons.
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PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
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PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
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PCMPEQ, PCMPGT,
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// ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
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ADD, SUB, ADC, SBB, SMUL,
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@ -77,14 +77,8 @@ def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
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def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
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def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
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def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
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def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
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def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
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def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
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def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
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def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
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def X86vshl : SDNode<"X86ISD::VSHL",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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@ -4092,35 +4092,35 @@ let Predicates = [HasAVX] in {
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defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d,
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VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
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def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
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def : Pat<(v16i8 (X86pcmpeq VR128:$src1, VR128:$src2)),
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(VPCMPEQBrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
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def : Pat<(v16i8 (X86pcmpeq VR128:$src1,
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(bc_v16i8 (memopv2i64 addr:$src2)))),
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(VPCMPEQBrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
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def : Pat<(v8i16 (X86pcmpeq VR128:$src1, VR128:$src2)),
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(VPCMPEQWrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
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def : Pat<(v8i16 (X86pcmpeq VR128:$src1,
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(bc_v8i16 (memopv2i64 addr:$src2)))),
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(VPCMPEQWrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86pcmpeq VR128:$src1, VR128:$src2)),
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(VPCMPEQDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
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def : Pat<(v4i32 (X86pcmpeq VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))),
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(VPCMPEQDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
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def : Pat<(v16i8 (X86pcmpgt VR128:$src1, VR128:$src2)),
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(VPCMPGTBrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
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def : Pat<(v16i8 (X86pcmpgt VR128:$src1,
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(bc_v16i8 (memopv2i64 addr:$src2)))),
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(VPCMPGTBrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
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def : Pat<(v8i16 (X86pcmpgt VR128:$src1, VR128:$src2)),
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(VPCMPGTWrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
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def : Pat<(v8i16 (X86pcmpgt VR128:$src1,
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(bc_v8i16 (memopv2i64 addr:$src2)))),
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(VPCMPGTWrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86pcmpgt VR128:$src1, VR128:$src2)),
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(VPCMPGTDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
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def : Pat<(v4i32 (X86pcmpgt VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))),
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(VPCMPGTDrm VR128:$src1, addr:$src2)>;
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}
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@ -4139,35 +4139,35 @@ let Predicates = [HasAVX2] in {
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defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d,
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VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
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def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)),
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def : Pat<(v32i8 (X86pcmpeq VR256:$src1, VR256:$src2)),
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(VPCMPEQBYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v32i8 (X86pcmpeqb VR256:$src1,
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def : Pat<(v32i8 (X86pcmpeq VR256:$src1,
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(bc_v32i8 (memopv4i64 addr:$src2)))),
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(VPCMPEQBYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)),
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def : Pat<(v16i16 (X86pcmpeq VR256:$src1, VR256:$src2)),
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(VPCMPEQWYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v16i16 (X86pcmpeqw VR256:$src1,
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def : Pat<(v16i16 (X86pcmpeq VR256:$src1,
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(bc_v16i16 (memopv4i64 addr:$src2)))),
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(VPCMPEQWYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)),
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def : Pat<(v8i32 (X86pcmpeq VR256:$src1, VR256:$src2)),
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(VPCMPEQDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86pcmpeqd VR256:$src1,
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def : Pat<(v8i32 (X86pcmpeq VR256:$src1,
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(bc_v8i32 (memopv4i64 addr:$src2)))),
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(VPCMPEQDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)),
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def : Pat<(v32i8 (X86pcmpgt VR256:$src1, VR256:$src2)),
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(VPCMPGTBYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v32i8 (X86pcmpgtb VR256:$src1,
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def : Pat<(v32i8 (X86pcmpgt VR256:$src1,
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(bc_v32i8 (memopv4i64 addr:$src2)))),
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(VPCMPGTBYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)),
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def : Pat<(v16i16 (X86pcmpgt VR256:$src1, VR256:$src2)),
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(VPCMPGTWYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v16i16 (X86pcmpgtw VR256:$src1,
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def : Pat<(v16i16 (X86pcmpgt VR256:$src1,
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(bc_v16i16 (memopv4i64 addr:$src2)))),
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(VPCMPGTWYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)),
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def : Pat<(v8i32 (X86pcmpgt VR256:$src1, VR256:$src2)),
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(VPCMPGTDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86pcmpgtd VR256:$src1,
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def : Pat<(v8i32 (X86pcmpgt VR256:$src1,
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(bc_v8i32 (memopv4i64 addr:$src2)))),
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(VPCMPGTDYrm VR256:$src1, addr:$src2)>;
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}
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@ -4188,35 +4188,35 @@ let Constraints = "$src1 = $dst" in {
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} // Constraints = "$src1 = $dst"
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let Predicates = [HasSSE2] in {
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def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
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def : Pat<(v16i8 (X86pcmpeq VR128:$src1, VR128:$src2)),
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(PCMPEQBrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
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def : Pat<(v16i8 (X86pcmpeq VR128:$src1,
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(bc_v16i8 (memopv2i64 addr:$src2)))),
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(PCMPEQBrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
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def : Pat<(v8i16 (X86pcmpeq VR128:$src1, VR128:$src2)),
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(PCMPEQWrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
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def : Pat<(v8i16 (X86pcmpeq VR128:$src1,
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(bc_v8i16 (memopv2i64 addr:$src2)))),
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(PCMPEQWrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86pcmpeq VR128:$src1, VR128:$src2)),
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(PCMPEQDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
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def : Pat<(v4i32 (X86pcmpeq VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))),
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(PCMPEQDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
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def : Pat<(v16i8 (X86pcmpgt VR128:$src1, VR128:$src2)),
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(PCMPGTBrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
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def : Pat<(v16i8 (X86pcmpgt VR128:$src1,
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(bc_v16i8 (memopv2i64 addr:$src2)))),
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(PCMPGTBrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
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def : Pat<(v8i16 (X86pcmpgt VR128:$src1, VR128:$src2)),
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(PCMPGTWrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
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def : Pat<(v8i16 (X86pcmpgt VR128:$src1,
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(bc_v8i16 (memopv2i64 addr:$src2)))),
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(PCMPGTWrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86pcmpgt VR128:$src1, VR128:$src2)),
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||||
(PCMPGTDrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
|
||||
def : Pat<(v4i32 (X86pcmpgt VR128:$src1,
|
||||
(bc_v4i32 (memopv2i64 addr:$src2)))),
|
||||
(PCMPGTDrm VR128:$src1, addr:$src2)>;
|
||||
}
|
||||
@ -6593,9 +6593,9 @@ let Predicates = [HasAVX] in {
|
||||
defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
|
||||
0>, VEX_4V;
|
||||
|
||||
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2i64 (X86pcmpeq VR128:$src1, VR128:$src2)),
|
||||
(VPCMPEQQrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
|
||||
def : Pat<(v2i64 (X86pcmpeq VR128:$src1, (memop addr:$src2))),
|
||||
(VPCMPEQQrm VR128:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
@ -6624,9 +6624,9 @@ let Predicates = [HasAVX2] in {
|
||||
defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
|
||||
int_x86_avx2_pmul_dq>, VEX_4V;
|
||||
|
||||
def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)),
|
||||
def : Pat<(v4i64 (X86pcmpeq VR256:$src1, VR256:$src2)),
|
||||
(VPCMPEQQYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))),
|
||||
def : Pat<(v4i64 (X86pcmpeq VR256:$src1, (memop addr:$src2))),
|
||||
(VPCMPEQQYrm VR256:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
@ -6646,9 +6646,9 @@ let Constraints = "$src1 = $dst" in {
|
||||
}
|
||||
|
||||
let Predicates = [HasSSE41] in {
|
||||
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2i64 (X86pcmpeq VR128:$src1, VR128:$src2)),
|
||||
(PCMPEQQrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
|
||||
def : Pat<(v2i64 (X86pcmpeq VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPEQQrm VR128:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
@ -6968,9 +6968,9 @@ let Predicates = [HasAVX] in {
|
||||
defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
|
||||
0>, VEX_4V;
|
||||
|
||||
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2i64 (X86pcmpgt VR128:$src1, VR128:$src2)),
|
||||
(VPCMPGTQrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
|
||||
def : Pat<(v2i64 (X86pcmpgt VR128:$src1, (memop addr:$src2))),
|
||||
(VPCMPGTQrm VR128:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
@ -6978,9 +6978,9 @@ let Predicates = [HasAVX2] in {
|
||||
defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>,
|
||||
VEX_4V;
|
||||
|
||||
def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)),
|
||||
def : Pat<(v4i64 (X86pcmpgt VR256:$src1, VR256:$src2)),
|
||||
(VPCMPGTQYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))),
|
||||
def : Pat<(v4i64 (X86pcmpgt VR256:$src1, (memop addr:$src2))),
|
||||
(VPCMPGTQYrm VR256:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
@ -6988,9 +6988,9 @@ let Constraints = "$src1 = $dst" in
|
||||
defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
|
||||
|
||||
let Predicates = [HasSSE42] in {
|
||||
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2i64 (X86pcmpgt VR128:$src1, VR128:$src2)),
|
||||
(PCMPGTQrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
|
||||
def : Pat<(v2i64 (X86pcmpgt VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPGTQrm VR128:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user