mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
compactify all of the integer conditional moves into one instruction that takes
a CC as an operand. Much smaller, much happier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
97f91027e6
commit
6788faa06a
@ -16,6 +16,7 @@
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#define TARGET_SPARCV8_H
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#include <iosfwd>
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#include <cassert>
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namespace llvm {
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@ -28,7 +29,6 @@ namespace llvm {
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TargetMachine &TM);
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FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
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FunctionPass *createSparcV8FPMoverPass(TargetMachine &TM);
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} // end namespace llvm;
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// Defines symbolic names for SparcV8 registers. This defines a mapping from
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@ -40,4 +40,114 @@ namespace llvm {
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//
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#include "SparcV8GenInstrNames.inc"
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namespace llvm {
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// Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
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// values must be kept in sync with the ones in the .td file.
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namespace V8CC {
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enum CondCodes {
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//ICC_A = 8 , // Always
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//ICC_N = 0 , // Never
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ICC_NE = 9 , // Not Equal
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ICC_E = 1 , // Equal
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ICC_G = 10 , // Greater
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ICC_LE = 2 , // Less or Equal
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ICC_GE = 11 , // Greater or Equal
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ICC_L = 3 , // Less
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ICC_GU = 12 , // Greater Unsigned
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ICC_LEU = 4 , // Less or Equal Unsigned
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ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
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ICC_CS = 5 , // Carry Set/Less Unsigned
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ICC_POS = 14 , // Positive
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ICC_NEG = 6 , // Negative
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ICC_VC = 15 , // Overflow Clear
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ICC_VS = 7 , // Overflow Set
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//FCC_A = 8+16, // Always
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//FCC_N = 0+16, // Never
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FCC_U = 7+16, // Unordered
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FCC_G = 6+16, // Greater
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FCC_UG = 5+16, // Unordered or Greater
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FCC_L = 4+16, // Less
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FCC_UL = 3+16, // Unordered or Less
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FCC_LG = 2+16, // Less or Greater
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FCC_NE = 1+16, // Not Equal
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FCC_E = 9+16, // Equal
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FCC_UE = 10+16, // Unordered or Equal
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FCC_GE = 11+16, // Greater or Equal
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FCC_UGE = 12+16, // Unordered or Greater or Equal
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FCC_LE = 13+16, // Less or Equal
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FCC_ULE = 14+16, // Unordered or Less or Equal
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FCC_O = 15+16, // Ordered
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};
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}
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static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case V8CC::ICC_NE: return V8::BNE;
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case V8CC::ICC_E: return V8::BE;
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case V8CC::ICC_G: return V8::BG;
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case V8CC::ICC_LE: return V8::BLE;
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case V8CC::ICC_GE: return V8::BGE;
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case V8CC::ICC_L: return V8::BL;
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case V8CC::ICC_GU: return V8::BGU;
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case V8CC::ICC_LEU: return V8::BLEU;
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case V8CC::ICC_CC: return V8::BCC;
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case V8CC::ICC_CS: return V8::BCS;
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case V8CC::ICC_POS: return V8::BPOS;
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case V8CC::ICC_NEG: return V8::BNEG;
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case V8CC::ICC_VC: return V8::BVC;
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case V8CC::ICC_VS: return V8::BVS;
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case V8CC::FCC_U: return V8::FBU;
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case V8CC::FCC_G: return V8::FBG;
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case V8CC::FCC_UG: return V8::FBUG;
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case V8CC::FCC_L: return V8::FBL;
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case V8CC::FCC_UL: return V8::FBUL;
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case V8CC::FCC_LG: return V8::FBLG;
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case V8CC::FCC_NE: return V8::FBNE;
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case V8CC::FCC_E: return V8::FBE;
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case V8CC::FCC_UE: return V8::FBUE;
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case V8CC::FCC_GE: return V8::FBGE;
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case V8CC::FCC_UGE: return V8::FBUGE;
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case V8CC::FCC_LE: return V8::FBLE;
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case V8CC::FCC_ULE: return V8::FBULE;
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case V8CC::FCC_O: return V8::FBO;
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}
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}
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static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case V8CC::ICC_NE: return "ne";
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case V8CC::ICC_E: return "e";
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case V8CC::ICC_G: return "g";
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case V8CC::ICC_LE: return "le";
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case V8CC::ICC_GE: return "ge";
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case V8CC::ICC_L: return "l";
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case V8CC::ICC_GU: return "gu";
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case V8CC::ICC_LEU: return "leu";
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case V8CC::ICC_CC: return "cc";
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case V8CC::ICC_CS: return "cs";
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case V8CC::ICC_POS: return "pos";
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case V8CC::ICC_NEG: return "neg";
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case V8CC::ICC_VC: return "vc";
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case V8CC::ICC_VS: return "vs";
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case V8CC::FCC_U: return "u";
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case V8CC::FCC_G: return "g";
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case V8CC::FCC_UG: return "ug";
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case V8CC::FCC_L: return "l";
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case V8CC::FCC_UL: return "ul";
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case V8CC::FCC_LG: return "lg";
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case V8CC::FCC_NE: return "ne";
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case V8CC::FCC_E: return "e";
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case V8CC::FCC_UE: return "ue";
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case V8CC::FCC_GE: return "ge";
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case V8CC::FCC_UGE: return "uge";
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case V8CC::FCC_LE: return "le";
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case V8CC::FCC_ULE: return "ule";
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case V8CC::FCC_O: return "o";
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}
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}
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} // end namespace llvm
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#endif
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@ -58,6 +58,8 @@ namespace {
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void printOperand(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum);
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void printV8CCOperand(const MachineInstr *MI, int opNum);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -211,6 +213,12 @@ void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
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}
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}
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void SparcV8AsmPrinter::printV8CCOperand(const MachineInstr *MI, int opNum) {
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int CC = (int)MI->getOperand(opNum).getImmedValue();
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O << SPARCCondCodeToString((V8CC::CondCodes)CC);
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}
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bool SparcV8AsmPrinter::doInitialization(Module &M) {
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Mang = new Mangler(M);
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@ -50,47 +50,6 @@ namespace V8ISD {
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};
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}
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// Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
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// values must be kept in sync with the ones in the .td file.
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namespace V8CC {
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enum CondCodes {
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//ICC_A = 8 , // Always
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//ICC_N = 0 , // Never
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ICC_NE = 9 , // Not Equal
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ICC_E = 1 , // Equal
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ICC_G = 10 , // Greater
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ICC_LE = 2 , // Less or Equal
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ICC_GE = 11 , // Greater or Equal
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ICC_L = 3 , // Less
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ICC_GU = 12 , // Greater Unsigned
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ICC_LEU = 4 , // Less or Equal Unsigned
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ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
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ICC_CS = 5 , // Carry Set/Less Unsigned
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ICC_POS = 14 , // Positive
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ICC_NEG = 6 , // Negative
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ICC_VC = 15 , // Overflow Clear
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ICC_VS = 7 , // Overflow Set
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//FCC_A = 8+16, // Always
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//FCC_N = 0+16, // Never
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FCC_U = 7+16, // Unordered
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FCC_G = 6+16, // Greater
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FCC_UG = 5+16, // Unordered or Greater
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FCC_L = 4+16, // Less
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FCC_UL = 3+16, // Unordered or Less
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FCC_LG = 2+16, // Less or Greater
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FCC_NE = 1+16, // Not Equal
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FCC_E = 9+16, // Equal
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FCC_UE = 10+16, // Unordered or Equal
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FCC_GE = 11+16, // Greater or Equal
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FCC_UGE = 12+16, // Unordered or Greater or Equal
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FCC_LE = 13+16, // Less or Equal
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FCC_ULE = 14+16, // Unordered or Less or Equal
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FCC_O = 15+16, // Ordered
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};
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}
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/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
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/// condition.
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static V8CC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
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@ -130,42 +89,6 @@ static V8CC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
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case ISD::SETUEQ: return V8CC::FCC_UE;
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}
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}
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static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case V8CC::ICC_NE: return V8::BNE;
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case V8CC::ICC_E: return V8::BE;
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case V8CC::ICC_G: return V8::BG;
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case V8CC::ICC_LE: return V8::BLE;
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case V8CC::ICC_GE: return V8::BGE;
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case V8CC::ICC_L: return V8::BL;
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case V8CC::ICC_GU: return V8::BGU;
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case V8CC::ICC_LEU: return V8::BLEU;
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case V8CC::ICC_CC: return V8::BCC;
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case V8CC::ICC_CS: return V8::BCS;
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case V8CC::ICC_POS: return V8::BPOS;
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case V8CC::ICC_NEG: return V8::BNEG;
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case V8CC::ICC_VC: return V8::BVC;
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case V8CC::ICC_VS: return V8::BVS;
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case V8CC::FCC_U: return V8::FBU;
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case V8CC::FCC_G: return V8::FBG;
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case V8CC::FCC_UG: return V8::FBUG;
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case V8CC::FCC_L: return V8::FBL;
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case V8CC::FCC_UL: return V8::FBUL;
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case V8CC::FCC_LG: return V8::FBLG;
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case V8CC::FCC_NE: return V8::FBNE;
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case V8CC::FCC_E: return V8::FBE;
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case V8CC::FCC_UE: return V8::FBUE;
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case V8CC::FCC_GE: return V8::FBGE;
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case V8CC::FCC_UGE: return V8::FBUGE;
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case V8CC::FCC_LE: return V8::FBLE;
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case V8CC::FCC_ULE: return V8::FBULE;
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case V8CC::FCC_O: return V8::FBO;
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}
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}
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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@ -86,6 +86,10 @@ def MEMri : Operand<i32> {
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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// Operand for printing out a condition code.
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let PrintMethod = "printV8CCOperand" in
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def V8CC : Operand<i32>;
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def SDTV8cmpfcc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8brcc :
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@ -212,12 +216,14 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
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imm:$Cond, ICC))]>;
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imm:$Cond, ICC))]>,
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Requires<[HasNoV9]>;
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def SELECT_CC_Int_FCC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond, FCC))]>;
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imm:$Cond, FCC))]>,
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Requires<[HasNoV9]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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@ -802,96 +808,27 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
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let Predicates = [HasV9], isTwoAddress = 1 in {
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// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
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// FIXME: Add instruction encodings for the JIT some day.
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class IntCMOVICCrr<string asmstr, ICC_VAL CC>
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
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def MOVICCrr
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
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int CondBits = CC.ICCVal;
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}
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class IntCMOVICCri<string asmstr, ICC_VAL CC>
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
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(V8selecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
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def MOVICCri
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc simm11:$F, IntRegs:$T, CC, ICC))]> {
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int CondBits = CC.ICCVal;
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}
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// MOV*rr instructions.
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def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
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def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
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def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
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def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>;
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def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>;
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def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>;
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def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>;
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def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>;
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def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>;
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def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>;
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def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>;
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def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
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def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
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def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
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// MOV*ri instructions.
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def MOVNEri : IntCMOVICCri< "movne %icc, $F, $dst", ICC_NE>;
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def MOVEri : IntCMOVICCri< "move %icc, $F, $dst", ICC_E>;
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def MOVGri : IntCMOVICCri< "movg %icc, $F, $dst", ICC_G>;
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def MOVLEri : IntCMOVICCri< "movle %icc, $F, $dst", ICC_LE>;
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def MOVGEri : IntCMOVICCri< "movge %icc, $F, $dst", ICC_GE>;
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def MOVLri : IntCMOVICCri< "movl %icc, $F, $dst", ICC_L>;
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def MOVGUri : IntCMOVICCri< "movgu %icc, $F, $dst", ICC_GU>;
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def MOVLEUri : IntCMOVICCri<"movleu %icc, $F, $dst", ICC_LEU>;
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def MOVCCri : IntCMOVICCri< "movcc %icc, $F, $dst", ICC_CC>;
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def MOVCSri : IntCMOVICCri< "movcs %icc, $F, $dst", ICC_CS>;
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def MOVPOSri : IntCMOVICCri<"movpos %icc, $F, $dst", ICC_POS>;
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def MOVNEGri : IntCMOVICCri<"movneg %icc, $F, $dst", ICC_NEG>;
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def MOVVCri : IntCMOVICCri< "movvc %icc, $F, $dst", ICC_VC>;
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def MOVVSri : IntCMOVICCri< "movvs %icc, $F, $dst", ICC_VS>;
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(V8selecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
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// FIXME: Allow regalloc of the fcc condition code some day.
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class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
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def MOVFCCrr
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
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"movf$cc %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
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int CondBits = CC.FCCVal;
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}
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class IntCMOVFCCri<string asmstr, FCC_VAL CC>
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
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(V8selectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
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def MOVFCCri
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
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"movf$cc %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc simm11:$F, IntRegs:$T, CC, FCC))]> {
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int CondBits = CC.FCCVal;
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}
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// MOVF*rr instructions.
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def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
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def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
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def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
|
||||
// MOVF*ri instructions.
|
||||
def MOVFUri : IntCMOVFCCri< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGri : IntCMOVFCCri< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGri : IntCMOVFCCri< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLri : IntCMOVFCCri< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULri : IntCMOVFCCri< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGri : IntCMOVFCCri< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNEri : IntCMOVFCCri< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFEri : IntCMOVFCCri< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUEri : IntCMOVFCCri< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGEri : IntCMOVFCCri< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGEri : IntCMOVFCCri<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLEri : IntCMOVFCCri< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULEri : IntCMOVFCCri<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOri : IntCMOVFCCri< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
(V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
|
||||
}
|
||||
|
||||
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
#define TARGET_SPARCV8_H
|
||||
|
||||
#include <iosfwd>
|
||||
#include <cassert>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
@ -28,7 +29,6 @@ namespace llvm {
|
||||
TargetMachine &TM);
|
||||
FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
|
||||
FunctionPass *createSparcV8FPMoverPass(TargetMachine &TM);
|
||||
|
||||
} // end namespace llvm;
|
||||
|
||||
// Defines symbolic names for SparcV8 registers. This defines a mapping from
|
||||
@ -40,4 +40,114 @@ namespace llvm {
|
||||
//
|
||||
#include "SparcV8GenInstrNames.inc"
|
||||
|
||||
|
||||
namespace llvm {
|
||||
// Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
|
||||
// values must be kept in sync with the ones in the .td file.
|
||||
namespace V8CC {
|
||||
enum CondCodes {
|
||||
//ICC_A = 8 , // Always
|
||||
//ICC_N = 0 , // Never
|
||||
ICC_NE = 9 , // Not Equal
|
||||
ICC_E = 1 , // Equal
|
||||
ICC_G = 10 , // Greater
|
||||
ICC_LE = 2 , // Less or Equal
|
||||
ICC_GE = 11 , // Greater or Equal
|
||||
ICC_L = 3 , // Less
|
||||
ICC_GU = 12 , // Greater Unsigned
|
||||
ICC_LEU = 4 , // Less or Equal Unsigned
|
||||
ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
|
||||
ICC_CS = 5 , // Carry Set/Less Unsigned
|
||||
ICC_POS = 14 , // Positive
|
||||
ICC_NEG = 6 , // Negative
|
||||
ICC_VC = 15 , // Overflow Clear
|
||||
ICC_VS = 7 , // Overflow Set
|
||||
|
||||
//FCC_A = 8+16, // Always
|
||||
//FCC_N = 0+16, // Never
|
||||
FCC_U = 7+16, // Unordered
|
||||
FCC_G = 6+16, // Greater
|
||||
FCC_UG = 5+16, // Unordered or Greater
|
||||
FCC_L = 4+16, // Less
|
||||
FCC_UL = 3+16, // Unordered or Less
|
||||
FCC_LG = 2+16, // Less or Greater
|
||||
FCC_NE = 1+16, // Not Equal
|
||||
FCC_E = 9+16, // Equal
|
||||
FCC_UE = 10+16, // Unordered or Equal
|
||||
FCC_GE = 11+16, // Greater or Equal
|
||||
FCC_UGE = 12+16, // Unordered or Greater or Equal
|
||||
FCC_LE = 13+16, // Less or Equal
|
||||
FCC_ULE = 14+16, // Unordered or Less or Equal
|
||||
FCC_O = 15+16, // Ordered
|
||||
};
|
||||
}
|
||||
|
||||
static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
|
||||
switch (CC) {
|
||||
default: assert(0 && "Unknown condition code");
|
||||
case V8CC::ICC_NE: return V8::BNE;
|
||||
case V8CC::ICC_E: return V8::BE;
|
||||
case V8CC::ICC_G: return V8::BG;
|
||||
case V8CC::ICC_LE: return V8::BLE;
|
||||
case V8CC::ICC_GE: return V8::BGE;
|
||||
case V8CC::ICC_L: return V8::BL;
|
||||
case V8CC::ICC_GU: return V8::BGU;
|
||||
case V8CC::ICC_LEU: return V8::BLEU;
|
||||
case V8CC::ICC_CC: return V8::BCC;
|
||||
case V8CC::ICC_CS: return V8::BCS;
|
||||
case V8CC::ICC_POS: return V8::BPOS;
|
||||
case V8CC::ICC_NEG: return V8::BNEG;
|
||||
case V8CC::ICC_VC: return V8::BVC;
|
||||
case V8CC::ICC_VS: return V8::BVS;
|
||||
case V8CC::FCC_U: return V8::FBU;
|
||||
case V8CC::FCC_G: return V8::FBG;
|
||||
case V8CC::FCC_UG: return V8::FBUG;
|
||||
case V8CC::FCC_L: return V8::FBL;
|
||||
case V8CC::FCC_UL: return V8::FBUL;
|
||||
case V8CC::FCC_LG: return V8::FBLG;
|
||||
case V8CC::FCC_NE: return V8::FBNE;
|
||||
case V8CC::FCC_E: return V8::FBE;
|
||||
case V8CC::FCC_UE: return V8::FBUE;
|
||||
case V8CC::FCC_GE: return V8::FBGE;
|
||||
case V8CC::FCC_UGE: return V8::FBUGE;
|
||||
case V8CC::FCC_LE: return V8::FBLE;
|
||||
case V8CC::FCC_ULE: return V8::FBULE;
|
||||
case V8CC::FCC_O: return V8::FBO;
|
||||
}
|
||||
}
|
||||
|
||||
static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
|
||||
switch (CC) {
|
||||
default: assert(0 && "Unknown condition code");
|
||||
case V8CC::ICC_NE: return "ne";
|
||||
case V8CC::ICC_E: return "e";
|
||||
case V8CC::ICC_G: return "g";
|
||||
case V8CC::ICC_LE: return "le";
|
||||
case V8CC::ICC_GE: return "ge";
|
||||
case V8CC::ICC_L: return "l";
|
||||
case V8CC::ICC_GU: return "gu";
|
||||
case V8CC::ICC_LEU: return "leu";
|
||||
case V8CC::ICC_CC: return "cc";
|
||||
case V8CC::ICC_CS: return "cs";
|
||||
case V8CC::ICC_POS: return "pos";
|
||||
case V8CC::ICC_NEG: return "neg";
|
||||
case V8CC::ICC_VC: return "vc";
|
||||
case V8CC::ICC_VS: return "vs";
|
||||
case V8CC::FCC_U: return "u";
|
||||
case V8CC::FCC_G: return "g";
|
||||
case V8CC::FCC_UG: return "ug";
|
||||
case V8CC::FCC_L: return "l";
|
||||
case V8CC::FCC_UL: return "ul";
|
||||
case V8CC::FCC_LG: return "lg";
|
||||
case V8CC::FCC_NE: return "ne";
|
||||
case V8CC::FCC_E: return "e";
|
||||
case V8CC::FCC_UE: return "ue";
|
||||
case V8CC::FCC_GE: return "ge";
|
||||
case V8CC::FCC_UGE: return "uge";
|
||||
case V8CC::FCC_LE: return "le";
|
||||
case V8CC::FCC_ULE: return "ule";
|
||||
case V8CC::FCC_O: return "o";
|
||||
}
|
||||
}
|
||||
} // end namespace llvm
|
||||
#endif
|
||||
|
||||
@ -58,6 +58,8 @@ namespace {
|
||||
|
||||
void printOperand(const MachineInstr *MI, int opNum);
|
||||
void printMemOperand(const MachineInstr *MI, int opNum);
|
||||
void printV8CCOperand(const MachineInstr *MI, int opNum);
|
||||
|
||||
bool printInstruction(const MachineInstr *MI); // autogenerated.
|
||||
bool runOnMachineFunction(MachineFunction &F);
|
||||
bool doInitialization(Module &M);
|
||||
@ -211,6 +213,12 @@ void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
|
||||
}
|
||||
}
|
||||
|
||||
void SparcV8AsmPrinter::printV8CCOperand(const MachineInstr *MI, int opNum) {
|
||||
int CC = (int)MI->getOperand(opNum).getImmedValue();
|
||||
O << SPARCCondCodeToString((V8CC::CondCodes)CC);
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool SparcV8AsmPrinter::doInitialization(Module &M) {
|
||||
Mang = new Mangler(M);
|
||||
|
||||
@ -50,47 +50,6 @@ namespace V8ISD {
|
||||
};
|
||||
}
|
||||
|
||||
// Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
|
||||
// values must be kept in sync with the ones in the .td file.
|
||||
namespace V8CC {
|
||||
enum CondCodes {
|
||||
//ICC_A = 8 , // Always
|
||||
//ICC_N = 0 , // Never
|
||||
ICC_NE = 9 , // Not Equal
|
||||
ICC_E = 1 , // Equal
|
||||
ICC_G = 10 , // Greater
|
||||
ICC_LE = 2 , // Less or Equal
|
||||
ICC_GE = 11 , // Greater or Equal
|
||||
ICC_L = 3 , // Less
|
||||
ICC_GU = 12 , // Greater Unsigned
|
||||
ICC_LEU = 4 , // Less or Equal Unsigned
|
||||
ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
|
||||
ICC_CS = 5 , // Carry Set/Less Unsigned
|
||||
ICC_POS = 14 , // Positive
|
||||
ICC_NEG = 6 , // Negative
|
||||
ICC_VC = 15 , // Overflow Clear
|
||||
ICC_VS = 7 , // Overflow Set
|
||||
|
||||
//FCC_A = 8+16, // Always
|
||||
//FCC_N = 0+16, // Never
|
||||
FCC_U = 7+16, // Unordered
|
||||
FCC_G = 6+16, // Greater
|
||||
FCC_UG = 5+16, // Unordered or Greater
|
||||
FCC_L = 4+16, // Less
|
||||
FCC_UL = 3+16, // Unordered or Less
|
||||
FCC_LG = 2+16, // Less or Greater
|
||||
FCC_NE = 1+16, // Not Equal
|
||||
FCC_E = 9+16, // Equal
|
||||
FCC_UE = 10+16, // Unordered or Equal
|
||||
FCC_GE = 11+16, // Greater or Equal
|
||||
FCC_UGE = 12+16, // Unordered or Greater or Equal
|
||||
FCC_LE = 13+16, // Less or Equal
|
||||
FCC_ULE = 14+16, // Unordered or Less or Equal
|
||||
FCC_O = 15+16, // Ordered
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
|
||||
/// condition.
|
||||
static V8CC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
|
||||
@ -130,42 +89,6 @@ static V8CC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
|
||||
case ISD::SETUEQ: return V8CC::FCC_UE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
|
||||
switch (CC) {
|
||||
default: assert(0 && "Unknown condition code");
|
||||
case V8CC::ICC_NE: return V8::BNE;
|
||||
case V8CC::ICC_E: return V8::BE;
|
||||
case V8CC::ICC_G: return V8::BG;
|
||||
case V8CC::ICC_LE: return V8::BLE;
|
||||
case V8CC::ICC_GE: return V8::BGE;
|
||||
case V8CC::ICC_L: return V8::BL;
|
||||
case V8CC::ICC_GU: return V8::BGU;
|
||||
case V8CC::ICC_LEU: return V8::BLEU;
|
||||
case V8CC::ICC_CC: return V8::BCC;
|
||||
case V8CC::ICC_CS: return V8::BCS;
|
||||
case V8CC::ICC_POS: return V8::BPOS;
|
||||
case V8CC::ICC_NEG: return V8::BNEG;
|
||||
case V8CC::ICC_VC: return V8::BVC;
|
||||
case V8CC::ICC_VS: return V8::BVS;
|
||||
case V8CC::FCC_U: return V8::FBU;
|
||||
case V8CC::FCC_G: return V8::FBG;
|
||||
case V8CC::FCC_UG: return V8::FBUG;
|
||||
case V8CC::FCC_L: return V8::FBL;
|
||||
case V8CC::FCC_UL: return V8::FBUL;
|
||||
case V8CC::FCC_LG: return V8::FBLG;
|
||||
case V8CC::FCC_NE: return V8::FBNE;
|
||||
case V8CC::FCC_E: return V8::FBE;
|
||||
case V8CC::FCC_UE: return V8::FBUE;
|
||||
case V8CC::FCC_GE: return V8::FBGE;
|
||||
case V8CC::FCC_UGE: return V8::FBUGE;
|
||||
case V8CC::FCC_LE: return V8::FBLE;
|
||||
case V8CC::FCC_ULE: return V8::FBULE;
|
||||
case V8CC::FCC_O: return V8::FBO;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
namespace {
|
||||
class SparcV8TargetLowering : public TargetLowering {
|
||||
|
||||
@ -86,6 +86,10 @@ def MEMri : Operand<i32> {
|
||||
def brtarget : Operand<OtherVT>;
|
||||
def calltarget : Operand<i32>;
|
||||
|
||||
// Operand for printing out a condition code.
|
||||
let PrintMethod = "printV8CCOperand" in
|
||||
def V8CC : Operand<i32>;
|
||||
|
||||
def SDTV8cmpfcc :
|
||||
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
|
||||
def SDTV8brcc :
|
||||
@ -212,12 +216,14 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_Int_ICC PSEUDO!",
|
||||
[(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
|
||||
imm:$Cond, ICC))]>;
|
||||
imm:$Cond, ICC))]>,
|
||||
Requires<[HasNoV9]>;
|
||||
def SELECT_CC_Int_FCC
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_Int_FCC PSEUDO!",
|
||||
[(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
|
||||
imm:$Cond, FCC))]>;
|
||||
imm:$Cond, FCC))]>,
|
||||
Requires<[HasNoV9]>;
|
||||
def SELECT_CC_FP_ICC
|
||||
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
|
||||
"; SELECT_CC_FP_ICC PSEUDO!",
|
||||
@ -802,96 +808,27 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
||||
let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
||||
// FIXME: Add instruction encodings for the JIT some day.
|
||||
class IntCMOVICCrr<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
|
||||
def MOVICCrr
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
|
||||
"mov$cc %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
class IntCMOVICCri<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
|
||||
def MOVICCri
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
|
||||
"mov$cc %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc simm11:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
|
||||
// MOV*rr instructions.
|
||||
def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
|
||||
def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>;
|
||||
def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>;
|
||||
def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>;
|
||||
def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>;
|
||||
def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>;
|
||||
def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>;
|
||||
def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>;
|
||||
def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>;
|
||||
def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
|
||||
// MOV*ri instructions.
|
||||
def MOVNEri : IntCMOVICCri< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVEri : IntCMOVICCri< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGri : IntCMOVICCri< "movg %icc, $F, $dst", ICC_G>;
|
||||
def MOVLEri : IntCMOVICCri< "movle %icc, $F, $dst", ICC_LE>;
|
||||
def MOVGEri : IntCMOVICCri< "movge %icc, $F, $dst", ICC_GE>;
|
||||
def MOVLri : IntCMOVICCri< "movl %icc, $F, $dst", ICC_L>;
|
||||
def MOVGUri : IntCMOVICCri< "movgu %icc, $F, $dst", ICC_GU>;
|
||||
def MOVLEUri : IntCMOVICCri<"movleu %icc, $F, $dst", ICC_LEU>;
|
||||
def MOVCCri : IntCMOVICCri< "movcc %icc, $F, $dst", ICC_CC>;
|
||||
def MOVCSri : IntCMOVICCri< "movcs %icc, $F, $dst", ICC_CS>;
|
||||
def MOVPOSri : IntCMOVICCri<"movpos %icc, $F, $dst", ICC_POS>;
|
||||
def MOVNEGri : IntCMOVICCri<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCri : IntCMOVICCri< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSri : IntCMOVICCri< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
(V8selecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
|
||||
|
||||
// FIXME: Allow regalloc of the fcc condition code some day.
|
||||
class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
|
||||
def MOVFCCrr
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
|
||||
"movf$cc %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
class IntCMOVFCCri<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
|
||||
def MOVFCCri
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
|
||||
"movf$cc %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc simm11:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
|
||||
// MOVF*rr instructions.
|
||||
def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
|
||||
// MOVF*ri instructions.
|
||||
def MOVFUri : IntCMOVFCCri< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGri : IntCMOVFCCri< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGri : IntCMOVFCCri< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLri : IntCMOVFCCri< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULri : IntCMOVFCCri< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGri : IntCMOVFCCri< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNEri : IntCMOVFCCri< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFEri : IntCMOVFCCri< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUEri : IntCMOVFCCri< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGEri : IntCMOVFCCri< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGEri : IntCMOVFCCri<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLEri : IntCMOVFCCri< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULEri : IntCMOVFCCri<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOri : IntCMOVFCCri< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
(V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
|
||||
}
|
||||
|
||||
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user