mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Add immediate forms of integer cmovs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
749d6fadf8
commit
97f91027e6
@ -800,17 +800,22 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
||||
|
||||
// V9 Conditional Moves.
|
||||
let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
||||
// FIXME: Add instruction encodings for the JIT some day.
|
||||
class IntCMOVICCrr<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
asmstr,
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
class IntCMOVICCri<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc simm11:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
|
||||
|
||||
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
||||
// MOV*rr instructions.
|
||||
def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
|
||||
@ -825,16 +830,38 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
|
||||
// MOV*ri instructions.
|
||||
def MOVNEri : IntCMOVICCri< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVEri : IntCMOVICCri< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGri : IntCMOVICCri< "movg %icc, $F, $dst", ICC_G>;
|
||||
def MOVLEri : IntCMOVICCri< "movle %icc, $F, $dst", ICC_LE>;
|
||||
def MOVGEri : IntCMOVICCri< "movge %icc, $F, $dst", ICC_GE>;
|
||||
def MOVLri : IntCMOVICCri< "movl %icc, $F, $dst", ICC_L>;
|
||||
def MOVGUri : IntCMOVICCri< "movgu %icc, $F, $dst", ICC_GU>;
|
||||
def MOVLEUri : IntCMOVICCri<"movleu %icc, $F, $dst", ICC_LEU>;
|
||||
def MOVCCri : IntCMOVICCri< "movcc %icc, $F, $dst", ICC_CC>;
|
||||
def MOVCSri : IntCMOVICCri< "movcs %icc, $F, $dst", ICC_CS>;
|
||||
def MOVPOSri : IntCMOVICCri<"movpos %icc, $F, $dst", ICC_POS>;
|
||||
def MOVNEGri : IntCMOVICCri<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCri : IntCMOVICCri< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSri : IntCMOVICCri< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
|
||||
// FIXME: Allow regalloc of the fcc condition code some day.
|
||||
class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
asmstr,
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
class IntCMOVFCCri<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc simm11:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
|
||||
// MOVF*rr instructions.
|
||||
def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
@ -849,6 +876,22 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
|
||||
// MOVF*ri instructions.
|
||||
def MOVFUri : IntCMOVFCCri< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGri : IntCMOVFCCri< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGri : IntCMOVFCCri< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLri : IntCMOVFCCri< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULri : IntCMOVFCCri< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGri : IntCMOVFCCri< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNEri : IntCMOVFCCri< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFEri : IntCMOVFCCri< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUEri : IntCMOVFCCri< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGEri : IntCMOVFCCri< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGEri : IntCMOVFCCri<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLEri : IntCMOVFCCri< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULEri : IntCMOVFCCri<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOri : IntCMOVFCCri< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
}
|
||||
|
||||
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
||||
|
@ -800,17 +800,22 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
||||
|
||||
// V9 Conditional Moves.
|
||||
let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
||||
// FIXME: Add instruction encodings for the JIT some day.
|
||||
class IntCMOVICCrr<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
asmstr,
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
class IntCMOVICCri<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc simm11:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
|
||||
|
||||
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
||||
// MOV*rr instructions.
|
||||
def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
|
||||
@ -825,16 +830,38 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
|
||||
// MOV*ri instructions.
|
||||
def MOVNEri : IntCMOVICCri< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVEri : IntCMOVICCri< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGri : IntCMOVICCri< "movg %icc, $F, $dst", ICC_G>;
|
||||
def MOVLEri : IntCMOVICCri< "movle %icc, $F, $dst", ICC_LE>;
|
||||
def MOVGEri : IntCMOVICCri< "movge %icc, $F, $dst", ICC_GE>;
|
||||
def MOVLri : IntCMOVICCri< "movl %icc, $F, $dst", ICC_L>;
|
||||
def MOVGUri : IntCMOVICCri< "movgu %icc, $F, $dst", ICC_GU>;
|
||||
def MOVLEUri : IntCMOVICCri<"movleu %icc, $F, $dst", ICC_LEU>;
|
||||
def MOVCCri : IntCMOVICCri< "movcc %icc, $F, $dst", ICC_CC>;
|
||||
def MOVCSri : IntCMOVICCri< "movcs %icc, $F, $dst", ICC_CS>;
|
||||
def MOVPOSri : IntCMOVICCri<"movpos %icc, $F, $dst", ICC_POS>;
|
||||
def MOVNEGri : IntCMOVICCri<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCri : IntCMOVICCri< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSri : IntCMOVICCri< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
|
||||
// FIXME: Allow regalloc of the fcc condition code some day.
|
||||
class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
asmstr,
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
class IntCMOVFCCri<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc simm11:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
|
||||
// MOVF*rr instructions.
|
||||
def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
@ -849,6 +876,22 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
|
||||
// MOVF*ri instructions.
|
||||
def MOVFUri : IntCMOVFCCri< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGri : IntCMOVFCCri< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGri : IntCMOVFCCri< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLri : IntCMOVFCCri< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULri : IntCMOVFCCri< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGri : IntCMOVFCCri< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNEri : IntCMOVFCCri< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFEri : IntCMOVFCCri< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUEri : IntCMOVFCCri< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGEri : IntCMOVFCCri< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGEri : IntCMOVFCCri<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLEri : IntCMOVFCCri< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULEri : IntCMOVFCCri<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOri : IntCMOVFCCri< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
}
|
||||
|
||||
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
||||
|
Loading…
Reference in New Issue
Block a user