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Hide more details in tablegen generated MCRegisterInfo ctor function.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-06-28 20:44:22 +00:00
parent 94b01f6882
commit 6844f7bcde
14 changed files with 20 additions and 32 deletions
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3
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -58,8 +58,7 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
const ARMSubtarget &sti)
: ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
BasePtr(ARM::R6) {

3
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@ -41,8 +41,7 @@
using namespace llvm;
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
: AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
TII(tii) {
}

3
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
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@ -38,8 +38,7 @@ using namespace llvm;
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
const TargetInstrInfo &tii)
: BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc,
BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
: BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
Subtarget(st),
TII(tii) {}

3
lib/Target/CellSPU/SPURegisterInfo.cpp
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@ -189,8 +189,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
const TargetInstrInfo &tii) :
SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
Subtarget(subtarget),
TII(tii)
{

3
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
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@ -45,8 +45,7 @@ using namespace llvm;
MBlazeRegisterInfo::
MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
: MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
: MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.

3
lib/Target/MSP430/MSP430RegisterInfo.cpp
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@ -35,8 +35,7 @@ using namespace llvm;
// FIXME: Provide proper call frame setup / destroy opcodes.
MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
const TargetInstrInfo &tii)
: MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc,
MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
: MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
TM(tm), TII(tii) {
StackAlign = TM.getFrameLowering()->getStackAlignment();
}

3
lib/Target/Mips/MipsRegisterInfo.cpp
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@ -44,8 +44,7 @@ using namespace llvm;
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
const TargetInstrInfo &tii)
: MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc,
Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.

2
lib/Target/PTX/PTXRegisterInfo.cpp
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@ -25,7 +25,7 @@ using namespace llvm;
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII)
: PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) {
: PTXGenRegisterInfo() {
}
void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,

3
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@ -114,8 +114,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
const TargetInstrInfo &tii)
: PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc,
PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;

3
lib/Target/Sparc/SparcRegisterInfo.cpp
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@ -32,8 +32,7 @@ using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii)
: SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
Subtarget(st), TII(tii) {
}

3
lib/Target/SystemZ/SystemZRegisterInfo.cpp
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@ -34,8 +34,7 @@ using namespace llvm;
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
const SystemZInstrInfo &tii)
: SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
: SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
TM(tm), TII(tii) {
}

3
lib/Target/X86/X86RegisterInfo.cpp
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@ -54,8 +54,7 @@ ForceStackAlign("force-align-stack",
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
const TargetInstrInfo &tii)
: X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
tm.getSubtarget<X86Subtarget>().is64Bit() ?
: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
X86::ADJCALLSTACKDOWN64 :
X86::ADJCALLSTACKDOWN32,
tm.getSubtarget<X86Subtarget>().is64Bit() ?

3
lib/Target/XCore/XCoreRegisterInfo.cpp
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@ -40,8 +40,7 @@
using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
: XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
: XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
TII(tii) {
}

14
utils/TableGen/RegisterInfoEmitter.cpp
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@ -215,8 +215,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName
<< "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
<< "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n"
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
@ -549,8 +548,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << " };\n";
// Emit extra information about registers.
const std::string &TargetName = Target.getName();
OS << "\n static const TargetRegisterInfoDesc "
<< Target.getName() << "RegInfoDesc[] = "
<< TargetName << "RegInfoDesc[] = "
<< "{ // Extra Descriptors\n";
OS << " { 0, 0 },\n";
@ -660,13 +660,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
<< "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(ID"
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
<< " SubRegIndexTable,\n"
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
<< " InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n"
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n"
<< "}\n\n";
// Collect all information about dwarf register numbers