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Lower unsigned vsetcc to psubus in certain cases
The current approach to lower a vsetult is to flip the sign bit of the
operands, swap the operands and then use a (signed) pcmpgt. psubus (unsigned
saturating subtract) can be used to emulate a vsetult more efficiently:
+ case ISD::SETULT: {
+ // If the comparison is against a constant we can turn this into a
+ // setule. With psubus, setule does not require a swap. This is
+ // beneficial because the constant in the register is no longer
+ // destructed as the destination so it can be hoisted out of a loop.
I also enable lowering via psubus in a few other cases where it's clearly
beneficial: setule and setuge if minu/maxu cannot be used.
rdar://problem/14338765
Patch by Adam Nemet <anemet@apple.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202301 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
parent
c540920a24
commit
685b0d9315
@ -10009,6 +10009,37 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
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DAG.getConstant(SSECC, MVT::i8));
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}
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/// \brief Try to turn a VSETULT into a VSETULE by modifying its second
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/// operand \p Op1. If non-trivial (for example because it's not constant)
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/// return an empty value.
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static SDValue ChangeVSETULTtoVSETULE(SDValue Op1, SelectionDAG &DAG)
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{
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BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
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if (!BV)
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return SDValue();
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MVT VT = Op1.getSimpleValueType();
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MVT EVT = VT.getVectorElementType();
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unsigned n = VT.getVectorNumElements();
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SmallVector<SDValue, 8> ULTOp1;
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for (unsigned i = 0; i < n; ++i) {
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ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
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if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
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return SDValue();
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// Avoid underflow.
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APInt Val = Elt->getAPIntValue();
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if (Val == 0)
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return SDValue();
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ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
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}
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op1), VT, ULTOp1.data(),
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ULTOp1.size());
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}
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static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDValue Op0 = Op.getOperand(0);
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@ -10080,6 +10111,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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// operations may be required for some comparisons.
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unsigned Opc;
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bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
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bool Subus = false;
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switch (SetCCOpcode) {
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default: llvm_unreachable("Unexpected SETCC condition");
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@ -10114,6 +10146,40 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
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}
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bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
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if (!MinMax && hasSubus) {
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// As another special case, use PSUBUS[BW] when it's profitable. E.g. for
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// Op0 u<= Op1:
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// t = psubus Op0, Op1
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// pcmpeq t, <0..0>
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETULT: {
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// If the comparison is against a constant we can turn this into a
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// setule. With psubus, setule does not require a swap. This is
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// beneficial because the constant in the register is no longer
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// destructed as the destination so it can be hoisted out of a loop.
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// Only do this pre-AVX since vpcmp* is no longer destructive.
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if (Subtarget->hasAVX())
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break;
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SDValue ULEOp1 = ChangeVSETULTtoVSETULE(Op1, DAG);
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if (ULEOp1.getNode()) {
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Op1 = ULEOp1;
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Subus = true; Invert = false; Swap = false;
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}
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break;
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}
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// Psubus is better than flip-sign because it requires no inversion.
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case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
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case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
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}
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if (Subus) {
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Opc = X86ISD::SUBUS;
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FlipSigns = false;
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}
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}
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if (Swap)
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std::swap(Op0, Op1);
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@ -10204,6 +10270,10 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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if (MinMax)
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Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
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if (Subus)
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Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
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getZeroVector(VT, Subtarget, DAG, dl));
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return Result;
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}
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95
test/CodeGen/X86/vec_setcc-2.ll
Normal file
95
test/CodeGen/X86/vec_setcc-2.ll
Normal file
@ -0,0 +1,95 @@
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; RUN: llc < %s -o - -mcpu=generic -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s
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; RUN: llc < %s -o - -mcpu=generic -mtriple=x86_64-apple-darwin -mattr=+sse4.2 | FileCheck %s
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; For a setult against a constant, turn it into a setule and lower via psubusw.
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define void @loop_no_const_reload(<2 x i64>* %in, <2 x i64>* %out, i32 %n) {
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; CHECK: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .short 25
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; CHECK-LABEL: loop_no_const_reload:
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; CHECK: psubusw
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; Constant is no longer clobbered so no need to reload it in the loop.
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; CHECK-NOT: movdqa {{%xmm[0-9]+}}, {{%xmm[0-9]+}}
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entry:
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%cmp9 = icmp eq i32 %n, 0
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br i1 %cmp9, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%arrayidx1 = getelementptr inbounds <2 x i64>* %in, i64 %indvars.iv
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%arrayidx1.val = load <2 x i64>* %arrayidx1, align 16
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%0 = bitcast <2 x i64> %arrayidx1.val to <8 x i16>
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%cmp.i.i = icmp ult <8 x i16> %0, <i16 26, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26>
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%sext.i.i = sext <8 x i1> %cmp.i.i to <8 x i16>
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%1 = bitcast <8 x i16> %sext.i.i to <2 x i64>
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%arrayidx5 = getelementptr inbounds <2 x i64>* %out, i64 %indvars.iv
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store <2 x i64> %1, <2 x i64>* %arrayidx5, align 16
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; Be careful if decrementing the constant would undeflow.
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define void @loop_const_folding_underflow(<2 x i64>* %in, <2 x i64>* %out, i32 %n) {
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; CHECK-NOT: .short 25
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; CHECK-LABEL: loop_const_folding_underflow:
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; CHECK-NOT: psubusw
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entry:
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%cmp9 = icmp eq i32 %n, 0
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br i1 %cmp9, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%arrayidx1 = getelementptr inbounds <2 x i64>* %in, i64 %indvars.iv
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%arrayidx1.val = load <2 x i64>* %arrayidx1, align 16
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%0 = bitcast <2 x i64> %arrayidx1.val to <8 x i16>
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%cmp.i.i = icmp ult <8 x i16> %0, <i16 0, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26, i16 26>
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%sext.i.i = sext <8 x i1> %cmp.i.i to <8 x i16>
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%1 = bitcast <8 x i16> %sext.i.i to <2 x i64>
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%arrayidx5 = getelementptr inbounds <2 x i64>* %out, i64 %indvars.iv
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store <2 x i64> %1, <2 x i64>* %arrayidx5, align 16
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; Test for PSUBUSB
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define <16 x i8> @test_ult_byte(<16 x i8> %a) {
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; CHECK: .space 16,10
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; CHECK-LABEL: test_ult_byte:
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; CHECK: psubus
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entry:
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%icmp = icmp ult <16 x i8> %a, <i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11>
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%sext = sext <16 x i1> %icmp to <16 x i8>
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ret <16 x i8> %sext
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}
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; Only do this when we can turn the comparison into a setule. I.e. not for
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; register operands.
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define <8 x i16> @test_ult_register(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_ult_register:
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; CHECK-NOT: psubus
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entry:
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%icmp = icmp ult <8 x i16> %a, %b
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%sext = sext <8 x i1> %icmp to <8 x i16>
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ret <8 x i16> %sext
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}
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@ -42,12 +42,9 @@ define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone s
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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; SSE2-LABEL: v8i16_icmp_uge:
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; SSE2: movdqa {{.*}}(%rip), %xmm2
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; SEE2: pxor %xmm2, %xmm0
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; SSE2: pxor %xmm1, %xmm2
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; SSE2: pcmpgtw %xmm0, %xmm2
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; SSE2: pcmpeqd %xmm0, %xmm0
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; SSE2: pxor %xmm2, %xmm0
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; SSE2: psubusw %xmm0, %xmm1
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; SEE2: pxor %xmm0, %xmm0
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; SSE2: pcmpeqw %xmm1, %xmm0
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; SSE41-LABEL: v8i16_icmp_uge:
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; SSE41: pmaxuw %xmm0, %xmm1
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@ -63,12 +60,9 @@ define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone s
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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; SSE2-LABEL: v8i16_icmp_ule:
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; SSE2: movdqa {{.*}}(%rip), %xmm2
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; SSE2: pxor %xmm2, %xmm1
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; SSE2: pxor %xmm2, %xmm0
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; SSE2: pcmpgtw %xmm1, %xmm0
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; SSE2: pcmpeqd %xmm1, %xmm1
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; SSE2: pxor %xmm0, %xmm1
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; SSE2: psubusw %xmm1, %xmm0
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; SSE2: pxor %xmm1, %xmm1
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; SSE2: pcmpeqw %xmm0, %xmm1
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; SSE2: movdqa %xmm1, %xmm0
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; SSE41-LABEL: v8i16_icmp_ule:
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