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implement aliases for div/idiv that have an explicit A register operand,
implementing rdar://8431864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1377,6 +1377,26 @@ def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
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def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
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def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
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// div and idiv aliases for explicit A register.
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def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
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def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
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def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
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def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
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def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
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def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
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def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
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def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
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def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
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def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
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def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
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def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
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def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
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def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
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def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
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def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
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// Various unary fpstack operations default to operating on on ST1.
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// For example, "fxch" -> "fxch %st(1)"
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def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
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@ -880,3 +880,20 @@ mov (%rsi), %gs // CHECK: movl (%rsi), %gs # encoding: [0x8e,0x2e]
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mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e]
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// rdar://8431864
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div %bl,%al
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div %bx,%ax
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div %ecx,%eax
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div 0xdeadbeef(%ebx,%ecx,8),%eax
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div 0x45,%eax
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div 0x7eed,%eax
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div 0xbabecafe,%eax
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div 0x12345678,%eax
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idiv %bl,%al
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idiv %bx,%ax
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idiv %ecx,%eax
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idiv 0xdeadbeef(%ebx,%ecx,8),%eax
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idiv 0x45,%eax
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idiv 0x7eed,%eax
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idiv 0xbabecafe,%eax
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idiv 0x12345678,%eax
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