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Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test

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just yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-10-13 01:17:33 +00:00
parent 54908dd72b
commit 6932643a37
2 changed files with 59 additions and 17 deletions
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38
lib/Target/ARM/ARMInstrVFP.td
View File

@ -427,28 +427,34 @@ def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
[/* For disassembly only; pattern left blank */]>;
let neverHasSideEffects = 1 in {
def VMOVD: ADuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
IIC_fpUNA64, "vmov", ".f64\t$dst, $a", []>;
def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
def VMOVS: ASuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
IIC_fpUNA32, "vmov", ".f32\t$dst, $a", []>;
def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
} // neverHasSideEffects
def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
[(set DPR:$dst, (fneg (f64 DPR:$a)))]>;
def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
[(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,(outs SPR:$dst), (ins SPR:$a),
IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
[(set SPR:$dst, (fneg SPR:$a))]>;
def VNEGS : ASuIn_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
[(set SPR:$Sd, (fneg SPR:$Sm))]>;
def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
[(set DPR:$dst, (fsqrt (f64 DPR:$a)))]>;
def VSQRTD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
[(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
[(set SPR:$dst, (fsqrt SPR:$a))]>;
def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
[(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
//===----------------------------------------------------------------------===//
// FP <-> GPR Copies. Int <-> FP Conversions.

38
test/MC/ARM/simple-fp-encoding.ll
View File

@ -134,7 +134,7 @@ declare double @fabsl(double)
define float @f16(float %a) nounwind {
entry:
; CHECK: f16
; This call generates a "bfc" instruction instead of "vabs.f32".
; FIXME: This call generates a "bfc" instruction instead of "vabs.f32".
%call = tail call float @fabsf(float %a)
ret float %call
}
@ -156,3 +156,39 @@ entry:
%conv = fpext float %a to double
ret double %conv
}
define double @f19(double %a) nounwind readnone {
entry:
; CHECK: f19
; CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
%sub = fsub double -0.000000e+00, %a
ret double %sub
}
define float @f20(float %a) nounwind readnone {
entry:
; CHECK: f20
; FIXME: This produces an 'eor' instruction.
%sub = fsub float -0.000000e+00, %a
ret float %sub
}
define double @f21(double %a) nounwind readnone {
entry:
; CHECK: f21
; CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
%call = tail call double @sqrtl(double %a) nounwind
ret double %call
}
declare double @sqrtl(double) readnone
define float @f22(float %a) nounwind readnone {
entry:
; CHECK: f22
; CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
%call = tail call float @sqrtf(float %a) nounwind
ret float %call
}
declare float @sqrtf(float) readnone