mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT emitter. Needs some major refactoring as these two code emitters are almost identical
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155810 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
9719cf329b
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6942f706aa
@ -488,7 +488,9 @@ namespace X86II {
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///
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static inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) {
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this form");
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case X86II::MRMInitReg:
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// FIXME: Remove this form.
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return -1;
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default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
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case X86II::Pseudo:
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case X86II::RawFrm:
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@ -68,6 +68,18 @@ namespace {
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return "X86 Machine Code Emitter";
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}
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void emitOpcodePrefix(uint64_t TSFlags, int MemOperand,
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const MachineInstr &MI,
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const MCInstrDesc *Desc) const;
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void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand,
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const MachineInstr &MI,
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const MCInstrDesc *Desc) const;
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void emitSegmentOverridePrefix(uint64_t TSFlags,
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int MemOperand,
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const MachineInstr &MI) const;
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void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
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void getAnalysisUsage(AnalysisUsage &AU) const {
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@ -596,11 +608,476 @@ static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II,
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return Desc;
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}
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/// Is16BitMemOperand - Return true if the specified instruction has
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/// a 16-bit memory operand. Op specifies the operand # of the memoperand.
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static bool Is16BitMemOperand(const MachineInstr &MI, unsigned Op) {
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const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
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const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
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if ((BaseReg.getReg() != 0 &&
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X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
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(IndexReg.getReg() != 0 &&
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X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
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return true;
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return false;
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}
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/// Is32BitMemOperand - Return true if the specified instruction has
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/// a 32-bit memory operand. Op specifies the operand # of the memoperand.
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static bool Is32BitMemOperand(const MachineInstr &MI, unsigned Op) {
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const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
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const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
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if ((BaseReg.getReg() != 0 &&
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X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
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(IndexReg.getReg() != 0 &&
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X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
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return true;
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return false;
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}
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/// Is64BitMemOperand - Return true if the specified instruction has
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/// a 64-bit memory operand. Op specifies the operand # of the memoperand.
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#ifndef NDEBUG
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static bool Is64BitMemOperand(const MachineInstr &MI, unsigned Op) {
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const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
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const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
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if ((BaseReg.getReg() != 0 &&
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X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
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(IndexReg.getReg() != 0 &&
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X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
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return true;
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return false;
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}
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#endif
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template<class CodeEmitter>
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void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
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int MemOperand,
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const MachineInstr &MI,
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const MCInstrDesc *Desc) const {
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// Emit the lock opcode prefix as needed.
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if (Desc->TSFlags & X86II::LOCK)
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MCE.emitByte(0xF0);
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// Emit segment override opcode prefix as needed.
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emitSegmentOverridePrefix(TSFlags, MemOperand, MI);
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// Emit the repeat opcode prefix as needed.
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if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
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MCE.emitByte(0xF3);
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// Emit the address size opcode prefix as needed.
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bool need_address_override;
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if (TSFlags & X86II::AdSize) {
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need_address_override = true;
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} else if (MemOperand == -1) {
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need_address_override = false;
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} else if (Is64BitMode) {
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assert(!Is16BitMemOperand(MI, MemOperand));
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need_address_override = Is32BitMemOperand(MI, MemOperand);
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} else {
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assert(!Is64BitMemOperand(MI, MemOperand));
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need_address_override = Is16BitMemOperand(MI, MemOperand);
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}
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if (need_address_override)
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MCE.emitByte(0x67);
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// Emit the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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MCE.emitByte(0x66);
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bool Need0FPrefix = false;
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switch (Desc->TSFlags & X86II::Op0Mask) {
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case X86II::TB: // Two-byte opcode prefix
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case X86II::T8: // 0F 38
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case X86II::TA: // 0F 3A
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case X86II::A6: // 0F A6
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case X86II::A7: // 0F A7
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Need0FPrefix = true;
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break;
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case X86II::REP: break; // already handled.
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case X86II::T8XS: // F3 0F 38
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case X86II::XS: // F3 0F
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MCE.emitByte(0xF3);
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Need0FPrefix = true;
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break;
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case X86II::T8XD: // F2 0F 38
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case X86II::TAXD: // F2 0F 3A
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case X86II::XD: // F2 0F
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MCE.emitByte(0xF2);
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Need0FPrefix = true;
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break;
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case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
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case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
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MCE.emitByte(0xD8+
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(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
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>> X86II::Op0Shift));
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break; // Two-byte opcode prefix
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default: llvm_unreachable("Invalid prefix!");
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case 0: break; // No prefix!
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}
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// Handle REX prefix.
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if (Is64BitMode) {
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if (unsigned REX = determineREX(MI))
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MCE.emitByte(0x40 | REX);
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}
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// 0x0F escape code must be emitted just before the opcode.
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if (Need0FPrefix)
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MCE.emitByte(0x0F);
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switch (Desc->TSFlags & X86II::Op0Mask) {
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case X86II::T8XD: // F2 0F 38
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case X86II::T8XS: // F3 0F 38
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case X86II::T8: // 0F 38
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MCE.emitByte(0x38);
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break;
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case X86II::TAXD: // F2 0F 38
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case X86II::TA: // 0F 3A
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MCE.emitByte(0x3A);
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break;
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case X86II::A6: // 0F A6
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MCE.emitByte(0xA6);
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break;
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case X86II::A7: // 0F A7
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MCE.emitByte(0xA7);
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break;
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}
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}
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static unsigned GetX86RegNum(const MachineOperand &MO) {
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return X86_MC::getX86RegNum(MO.getReg());
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}
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// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
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// 0-7 and the difference between the 2 groups is given by the REX prefix.
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// In the VEX prefix, registers are seen sequencially from 0-15 and encoded
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// in 1's complement form, example:
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//
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// ModRM field => XMM9 => 1
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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static unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
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unsigned OpNum) {
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unsigned SrcReg = MI.getOperand(OpNum).getReg();
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unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
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if (X86II::isX86_64ExtendedReg(SrcReg))
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SrcRegNum |= 8;
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// The registers represented through VEX_VVVV should
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// be encoded in 1's complement form.
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return (~SrcRegNum) & 0xf;
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}
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/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
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template<class CodeEmitter>
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void Emitter<CodeEmitter>::emitSegmentOverridePrefix(uint64_t TSFlags,
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int MemOperand,
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const MachineInstr &MI) const {
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switch (TSFlags & X86II::SegOvrMask) {
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default: llvm_unreachable("Invalid segment!");
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case 0:
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// No segment override, check for explicit one on memory operand.
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if (MemOperand != -1) { // If the instruction has a memory operand.
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switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
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default: llvm_unreachable("Unknown segment register!");
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case 0: break;
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case X86::CS: MCE.emitByte(0x2E); break;
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case X86::SS: MCE.emitByte(0x36); break;
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case X86::DS: MCE.emitByte(0x3E); break;
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case X86::ES: MCE.emitByte(0x26); break;
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case X86::FS: MCE.emitByte(0x64); break;
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case X86::GS: MCE.emitByte(0x65); break;
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}
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}
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break;
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case X86II::FS:
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MCE.emitByte(0x64);
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break;
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case X86II::GS:
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MCE.emitByte(0x65);
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break;
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}
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}
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template<class CodeEmitter>
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void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
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int MemOperand,
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const MachineInstr &MI,
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const MCInstrDesc *Desc) const {
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
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// VEX_R: opcode externsion equivalent to REX.R in
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// 1's complement (inverted) form
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//
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// 1: Same as REX_R=0 (must be 1 in 32-bit mode)
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// 0: Same as REX_R=1 (64 bit mode only)
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//
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unsigned char VEX_R = 0x1;
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// VEX_X: equivalent to REX.X, only used when a
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// register is used for index in SIB Byte.
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//
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// 1: Same as REX.X=0 (must be 1 in 32-bit mode)
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// 0: Same as REX.X=1 (64-bit mode only)
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unsigned char VEX_X = 0x1;
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// VEX_B:
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//
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// 1: Same as REX_B=0 (ignored in 32-bit mode)
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// 0: Same as REX_B=1 (64 bit mode only)
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//
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unsigned char VEX_B = 0x1;
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// VEX_W: opcode specific (use like REX.W, or used for
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// opcode extension, or ignored, depending on the opcode byte)
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unsigned char VEX_W = 0;
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// XOP: Use XOP prefix byte 0x8f instead of VEX.
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unsigned char XOP = 0;
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// VEX_5M (VEX m-mmmmm field):
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//
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// 0b00000: Reserved for future use
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// 0b00001: implied 0F leading opcode
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// 0b00010: implied 0F 38 leading opcode bytes
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// 0b00011: implied 0F 3A leading opcode bytes
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// 0b00100-0b11111: Reserved for future use
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// 0b01000: XOP map select - 08h instructions with imm byte
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// 0b10001: XOP map select - 09h instructions with no imm byte
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unsigned char VEX_5M = 0x1;
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// VEX_4V (VEX vvvv field): a register specifier
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// (in 1's complement form) or 1111 if unused.
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unsigned char VEX_4V = 0xf;
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// VEX_L (Vector Length):
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//
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// 0: scalar or 128-bit vector
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// 1: 256-bit vector
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//
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unsigned char VEX_L = 0;
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// VEX_PP: opcode extension providing equivalent
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// functionality of a SIMD prefix
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//
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// 0b00: None
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// 0b01: 66
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// 0b10: F3
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// 0b11: F2
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//
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unsigned char VEX_PP = 0;
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// Encode the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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VEX_PP = 0x01;
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
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VEX_W = 1;
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if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
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XOP = 1;
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
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VEX_L = 1;
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switch (TSFlags & X86II::Op0Mask) {
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default: llvm_unreachable("Invalid prefix!");
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case X86II::T8: // 0F 38
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VEX_5M = 0x2;
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break;
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case X86II::TA: // 0F 3A
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VEX_5M = 0x3;
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break;
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case X86II::T8XS: // F3 0F 38
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VEX_PP = 0x2;
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VEX_5M = 0x2;
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break;
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case X86II::T8XD: // F2 0F 38
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VEX_PP = 0x3;
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VEX_5M = 0x2;
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break;
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case X86II::TAXD: // F2 0F 3A
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VEX_PP = 0x3;
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VEX_5M = 0x3;
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break;
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case X86II::XS: // F3 0F
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VEX_PP = 0x2;
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break;
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case X86II::XD: // F2 0F
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VEX_PP = 0x3;
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break;
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case X86II::XOP8:
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VEX_5M = 0x8;
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break;
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case X86II::XOP9:
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VEX_5M = 0x9;
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break;
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case X86II::A6: // Bypass: Not used by VEX
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case X86II::A7: // Bypass: Not used by VEX
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case X86II::TB: // Bypass: Not used by VEX
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case 0:
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break; // No prefix!
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}
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// Set the vector length to 256-bit if YMM0-YMM15 is used
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for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
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if (!MI.getOperand(i).isReg())
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continue;
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unsigned SrcReg = MI.getOperand(i).getReg();
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if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
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VEX_L = 1;
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}
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// Classify VEX_B, VEX_4V, VEX_R, VEX_X
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unsigned CurOp = 0;
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
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case X86II::MRMDestMem: {
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// MRMDestMem instructions forms:
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// MemAddr, src1(ModR/M)
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// MemAddr, src1(VEX_4V), src2(ModR/M)
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// MemAddr, src1(ModR/M), imm8
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//
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if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
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VEX_B = 0x0;
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if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
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VEX_X = 0x0;
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CurOp = X86::AddrNumOperands;
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
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const MachineOperand &MO = MI.getOperand(CurOp);
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if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
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VEX_R = 0x0;
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break;
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}
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case X86II::MRMSrcMem:
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// MRMSrcMem instructions forms:
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// src1(ModR/M), MemAddr
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// src1(ModR/M), src2(VEX_4V), MemAddr
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// src1(ModR/M), MemAddr, imm8
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// src1(ModR/M), MemAddr, src2(VEX_I8IMM)
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//
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// FMA4:
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// dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
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// dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
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if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
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VEX_R = 0x0;
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, 1);
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if (X86II::isX86_64ExtendedReg(
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MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
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VEX_B = 0x0;
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if (X86II::isX86_64ExtendedReg(
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MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
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VEX_X = 0x0;
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if (HasVEX_4VOp3)
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VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1);
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break;
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m: {
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// MRM[0-9]m instructions forms:
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// MemAddr
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||||
// src1(VEX_4V), MemAddr
|
||||
if (HasVEX_4V)
|
||||
VEX_4V = getVEXRegisterEncoding(MI, 0);
|
||||
|
||||
if (X86II::isX86_64ExtendedReg(
|
||||
MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
|
||||
VEX_B = 0x0;
|
||||
if (X86II::isX86_64ExtendedReg(
|
||||
MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
|
||||
VEX_X = 0x0;
|
||||
break;
|
||||
}
|
||||
case X86II::MRMSrcReg:
|
||||
// MRMSrcReg instructions forms:
|
||||
// dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
|
||||
// dst(ModR/M), src1(ModR/M)
|
||||
// dst(ModR/M), src1(ModR/M), imm8
|
||||
//
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_R = 0x0;
|
||||
CurOp++;
|
||||
|
||||
if (HasVEX_4V)
|
||||
VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_B = 0x0;
|
||||
CurOp++;
|
||||
if (HasVEX_4VOp3)
|
||||
VEX_4V = getVEXRegisterEncoding(MI, CurOp);
|
||||
break;
|
||||
case X86II::MRMDestReg:
|
||||
// MRMDestReg instructions forms:
|
||||
// dst(ModR/M), src(ModR/M)
|
||||
// dst(ModR/M), src(ModR/M), imm8
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
|
||||
VEX_B = 0x0;
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
|
||||
VEX_R = 0x0;
|
||||
break;
|
||||
case X86II::MRM0r: case X86II::MRM1r:
|
||||
case X86II::MRM2r: case X86II::MRM3r:
|
||||
case X86II::MRM4r: case X86II::MRM5r:
|
||||
case X86II::MRM6r: case X86II::MRM7r:
|
||||
// MRM0r-MRM7r instructions forms:
|
||||
// dst(VEX_4V), src(ModR/M), imm8
|
||||
VEX_4V = getVEXRegisterEncoding(MI, 0);
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
|
||||
VEX_B = 0x0;
|
||||
break;
|
||||
default: // RawFrm
|
||||
break;
|
||||
}
|
||||
|
||||
// Emit segment override opcode prefix as needed.
|
||||
emitSegmentOverridePrefix(TSFlags, MemOperand, MI);
|
||||
|
||||
// VEX opcode prefix can have 2 or 3 bytes
|
||||
//
|
||||
// 3 bytes:
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// 2 bytes:
|
||||
// +-----+ +-------------------+
|
||||
// | C5h | | R | vvvv | L | pp |
|
||||
// +-----+ +-------------------+
|
||||
//
|
||||
unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
|
||||
|
||||
if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
|
||||
MCE.emitByte(0xC5);
|
||||
MCE.emitByte(LastByte | (VEX_R << 7));
|
||||
return;
|
||||
}
|
||||
|
||||
// 3 byte VEX prefix
|
||||
MCE.emitByte(XOP ? 0x8F : 0xC4);
|
||||
MCE.emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M);
|
||||
MCE.emitByte(LastByte | (VEX_W << 7));
|
||||
}
|
||||
|
||||
template<class CodeEmitter>
|
||||
void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
|
||||
const MCInstrDesc *Desc) {
|
||||
DEBUG(dbgs() << MI);
|
||||
|
||||
|
||||
// If this is a pseudo instruction, lower it.
|
||||
switch (Desc->getOpcode()) {
|
||||
case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break;
|
||||
@ -621,99 +1098,12 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
|
||||
case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
|
||||
case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
|
||||
}
|
||||
|
||||
|
||||
|
||||
MCE.processDebugLoc(MI.getDebugLoc(), true);
|
||||
|
||||
unsigned Opcode = Desc->Opcode;
|
||||
|
||||
// Emit the lock opcode prefix as needed.
|
||||
if (Desc->TSFlags & X86II::LOCK)
|
||||
MCE.emitByte(0xF0);
|
||||
|
||||
// Emit segment override opcode prefix as needed.
|
||||
switch (Desc->TSFlags & X86II::SegOvrMask) {
|
||||
case X86II::FS:
|
||||
MCE.emitByte(0x64);
|
||||
break;
|
||||
case X86II::GS:
|
||||
MCE.emitByte(0x65);
|
||||
break;
|
||||
default: llvm_unreachable("Invalid segment!");
|
||||
case 0: break; // No segment override!
|
||||
}
|
||||
|
||||
// Emit the repeat opcode prefix as needed.
|
||||
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
|
||||
MCE.emitByte(0xF3);
|
||||
|
||||
// Emit the operand size opcode prefix as needed.
|
||||
if (Desc->TSFlags & X86II::OpSize)
|
||||
MCE.emitByte(0x66);
|
||||
|
||||
// Emit the address size opcode prefix as needed.
|
||||
if (Desc->TSFlags & X86II::AdSize)
|
||||
MCE.emitByte(0x67);
|
||||
|
||||
bool Need0FPrefix = false;
|
||||
switch (Desc->TSFlags & X86II::Op0Mask) {
|
||||
case X86II::TB: // Two-byte opcode prefix
|
||||
case X86II::T8: // 0F 38
|
||||
case X86II::TA: // 0F 3A
|
||||
case X86II::A6: // 0F A6
|
||||
case X86II::A7: // 0F A7
|
||||
Need0FPrefix = true;
|
||||
break;
|
||||
case X86II::REP: break; // already handled.
|
||||
case X86II::T8XS: // F3 0F 38
|
||||
case X86II::XS: // F3 0F
|
||||
MCE.emitByte(0xF3);
|
||||
Need0FPrefix = true;
|
||||
break;
|
||||
case X86II::T8XD: // F2 0F 38
|
||||
case X86II::TAXD: // F2 0F 3A
|
||||
case X86II::XD: // F2 0F
|
||||
MCE.emitByte(0xF2);
|
||||
Need0FPrefix = true;
|
||||
break;
|
||||
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
|
||||
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
|
||||
MCE.emitByte(0xD8+
|
||||
(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
|
||||
>> X86II::Op0Shift));
|
||||
break; // Two-byte opcode prefix
|
||||
default: llvm_unreachable("Invalid prefix!");
|
||||
case 0: break; // No prefix!
|
||||
}
|
||||
|
||||
// Handle REX prefix.
|
||||
if (Is64BitMode) {
|
||||
if (unsigned REX = determineREX(MI))
|
||||
MCE.emitByte(0x40 | REX);
|
||||
}
|
||||
|
||||
// 0x0F escape code must be emitted just before the opcode.
|
||||
if (Need0FPrefix)
|
||||
MCE.emitByte(0x0F);
|
||||
|
||||
switch (Desc->TSFlags & X86II::Op0Mask) {
|
||||
case X86II::T8XD: // F2 0F 38
|
||||
case X86II::T8XS: // F3 0F 38
|
||||
case X86II::T8: // 0F 38
|
||||
MCE.emitByte(0x38);
|
||||
break;
|
||||
case X86II::TAXD: // F2 0F 38
|
||||
case X86II::TA: // 0F 3A
|
||||
MCE.emitByte(0x3A);
|
||||
break;
|
||||
case X86II::A6: // 0F A6
|
||||
MCE.emitByte(0xA6);
|
||||
break;
|
||||
case X86II::A7: // 0F A7
|
||||
MCE.emitByte(0xA7);
|
||||
break;
|
||||
}
|
||||
|
||||
// If this is a two-address instruction, skip one of the register operands.
|
||||
unsigned NumOps = Desc->getNumOperands();
|
||||
unsigned CurOp = 0;
|
||||
@ -723,8 +1113,26 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
|
||||
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
|
||||
--NumOps;
|
||||
|
||||
uint64_t TSFlags = Desc->TSFlags;
|
||||
|
||||
// Is this instruction encoded using the AVX VEX prefix?
|
||||
bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
|
||||
// It uses the VEX.VVVV field?
|
||||
bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
|
||||
bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
|
||||
bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
|
||||
|
||||
// Determine where the memory operand starts, if present.
|
||||
int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
|
||||
if (MemoryOperand != -1) MemoryOperand += CurOp;
|
||||
|
||||
if (!HasVEXPrefix)
|
||||
emitOpcodePrefix(TSFlags, MemoryOperand, MI, Desc);
|
||||
else
|
||||
emitVEXOpcodePrefix(TSFlags, MemoryOperand, MI, Desc);
|
||||
|
||||
unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
|
||||
switch (Desc->TSFlags & X86II::FormMask) {
|
||||
switch (TSFlags & X86II::FormMask) {
|
||||
default:
|
||||
llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
|
||||
case X86II::Pseudo:
|
||||
@ -862,36 +1270,59 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
|
||||
}
|
||||
case X86II::MRMDestMem: {
|
||||
MCE.emitByte(BaseOpcode);
|
||||
|
||||
unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
|
||||
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
SrcRegNum++;
|
||||
emitMemModRMByte(MI, CurOp,
|
||||
X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
|
||||
.getReg()));
|
||||
CurOp += X86::AddrNumOperands + 1;
|
||||
X86_MC::getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
|
||||
CurOp = SrcRegNum + 1;
|
||||
if (CurOp != NumOps)
|
||||
emitConstant(MI.getOperand(CurOp++).getImm(),
|
||||
X86II::getSizeOfImm(Desc->TSFlags));
|
||||
break;
|
||||
}
|
||||
|
||||
case X86II::MRMSrcReg:
|
||||
case X86II::MRMSrcReg: {
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
|
||||
|
||||
unsigned SrcRegNum = CurOp+1;
|
||||
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
SrcRegNum++;
|
||||
|
||||
if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
|
||||
SrcRegNum++;
|
||||
|
||||
emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(),
|
||||
X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
|
||||
CurOp += 2;
|
||||
// 2 operands skipped with HasMemOp4, comensate accordingly
|
||||
CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
|
||||
if (HasVEX_4VOp3)
|
||||
++CurOp;
|
||||
if (CurOp != NumOps)
|
||||
emitConstant(MI.getOperand(CurOp++).getImm(),
|
||||
X86II::getSizeOfImm(Desc->TSFlags));
|
||||
break;
|
||||
|
||||
}
|
||||
case X86II::MRMSrcMem: {
|
||||
int AddrOperands = X86::AddrNumOperands;
|
||||
unsigned FirstMemOp = CurOp+1;
|
||||
if (HasVEX_4V) {
|
||||
++AddrOperands;
|
||||
++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
|
||||
}
|
||||
if(HasMemOp4) // Skip second register source (encoded in I8IMM)
|
||||
++FirstMemOp;
|
||||
|
||||
MCE.emitByte(BaseOpcode);
|
||||
|
||||
intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
|
||||
X86II::getSizeOfImm(Desc->TSFlags) : 0;
|
||||
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitMemModRMByte(MI, CurOp+1,
|
||||
emitMemModRMByte(MI, FirstMemOp,
|
||||
X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
|
||||
CurOp += AddrOperands + 1;
|
||||
if (HasVEX_4VOp3)
|
||||
++CurOp;
|
||||
if (CurOp != NumOps)
|
||||
emitConstant(MI.getOperand(CurOp++).getImm(),
|
||||
X86II::getSizeOfImm(Desc->TSFlags));
|
||||
@ -902,6 +1333,8 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
|
||||
case X86II::MRM2r: case X86II::MRM3r:
|
||||
case X86II::MRM4r: case X86II::MRM5r:
|
||||
case X86II::MRM6r: case X86II::MRM7r: {
|
||||
if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
|
||||
CurOp++;
|
||||
MCE.emitByte(BaseOpcode);
|
||||
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
|
||||
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
|
||||
@ -937,6 +1370,8 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
|
||||
case X86II::MRM2m: case X86II::MRM3m:
|
||||
case X86II::MRM4m: case X86II::MRM5m:
|
||||
case X86II::MRM6m: case X86II::MRM7m: {
|
||||
if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
|
||||
CurOp++;
|
||||
intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
|
||||
(MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
|
||||
X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
|
||||
|
Loading…
Reference in New Issue
Block a user