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[AArch64] Adjusts Cortex-A57 machine model to handle zero shift.

Browse Source 
http://reviews.llvm.org/D8043
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2015-04-10 13:19:21 +00:00
parent c8eb88e744
commit 694883f0f7
1 changed files with 9 additions and 0 deletions
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9
lib/Target/AArch64/AArch64SchedA57.td
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@ -127,6 +127,15 @@ def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
// Shifted Register with Shift == 0
// ----------------------------------------------------------------------------
def A57WriteISReg : SchedWriteVariant<[
SchedVar<RegShiftedPred, [WriteISReg]>,
SchedVar<NoSchedPred, [WriteI]>]>;
def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
// Divide and Multiply Instructions
// -----------------------------------------------------------------------------