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Add missing encoding information for some of the GPR<->FP register moves.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-29 23:15:25 +00:00
parent abd3f60859
commit 694e0ffb8a
2 changed files with 26 additions and 2 deletions
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25
lib/Target/ARM/ARMInstrVFP.td
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@ -513,9 +513,19 @@ def VMOVRRD : AVConv3I<0b11000101, 0b1011,
}
def VMOVRRS : AVConv3I<0b11000101, 0b1010,
(outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
(outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
[/* For disassembly only; pattern left blank */]> {
bits<5> src1;
bits<4> Rt;
bits<4> Rt2;
// Encode instruction operands.
let Inst{3-0} = src1{3-0};
let Inst{5} = src1{4};
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{7-6} = 0b00;
// Some single precision VFP instructions may be executed on both NEON and VFP
@ -555,6 +565,17 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
(outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
[/* For disassembly only; pattern left blank */]> {
// Instruction operands.
bits<5> dst1;
bits<4> src1;
bits<4> src2;
// Encode instruction operands.
let Inst{3-0} = dst1{3-0};
let Inst{5} = dst1{4};
let Inst{15-12} = src1;
let Inst{19-16} = src2;
let Inst{7-6} = 0b00;
// Some single precision VFP instructions may be executed on both NEON and VFP

3
test/MC/ARM/simple-fp-encoding.s
View File

@ -234,3 +234,6 @@
vcvtr.s32.f32 s0, s1
vcvtr.u32.f64 s0, d0
vcvtr.u32.f32 s0, s1
@ CHECK: vmovne s25, s26, r2, r5
vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]