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Use the correct shift amount type.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126684 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-02-28 21:10:10 +00:00
parent c6d160bfa2
commit 6973289208
1 changed files with 1 additions and 1 deletions
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lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -226,7 +226,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
DAG.getConstant(DiffBits, TLI.getPointerTy()));
DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
}
SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {