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[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2013-09-22 09:18:26 +00:00
parent a432a97b62
commit 69ae8f1abd
2 changed files with 105 additions and 29 deletions
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56
lib/Target/Sparc/SparcInstrFormats.td
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@ -149,3 +149,59 @@ multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
!strconcat(OpcStr, " $rs, $shcnt, $rd"),
[(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
}
class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSP<outs, ins, asmstr, pattern> {
bits<5> rd;
let op = 2;
let Inst{29-25} = rd;
let Inst{24-19} = op3;
}
class F4_1<bits<6> op3, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
bits<3> cc;
bits<4> cond;
bits<5> rs2;
let Inst{4-0} = rs2;
let Inst{11} = cc{0};
let Inst{12} = cc{1};
let Inst{13} = 0;
let Inst{17-14} = cond;
let Inst{18} = cc{2};
}
class F4_2<bits<6> op3, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
bits<3> cc;
bits<4> cond;
bits<11> simm11;
let Inst{10-0} = simm11;
let Inst{11} = cc{0};
let Inst{12} = cc{1};
let Inst{13} = 1;
let Inst{17-14} = cond;
let Inst{18} = cc{2};
}
class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
bits<4> cond;
bits<3> opf_cc;
bits<5> rs2;
let Inst{18} = 0;
let Inst{17-14} = cond;
let Inst{13-11} = opf_cc;
let Inst{10-5} = opf_low;
let Inst{4-0} = rs2;
}

78
lib/Target/Sparc/SparcInstrInfo.td
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@ -858,49 +858,69 @@ let Uses = [O6], isCall = 1 in
// V9 Conditional Moves.
let Predicates = [HasV9], Constraints = "$f = $rd" in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
// FIXME: Add instruction encodings for the JIT some day.
let Uses = [ICC] in {
let Uses = [ICC], cc = 0b100 in {
def MOVICCrr
: Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
"mov$cc %icc, $rs2, $rd",
[(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>;
: F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
"mov$cond %icc, $rs2, $rd",
[(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
def MOVICCri
: Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
"mov$cc %icc, $i, $rd",
[(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>;
: F4_2<0b101100, (outs IntRegs:$rd),
(ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
"mov$cond %icc, $simm11, $rd",
[(set i32:$rd,
(SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
}
let Uses = [FCC] in {
let Uses = [FCC], cc = 0b000 in {
def MOVFCCrr
: Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
"mov$cc %fcc0, $rs2, $rd",
[(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>;
: F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
"mov$cond %fcc0, $rs2, $rd",
[(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
def MOVFCCri
: Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
"mov$cc %fcc0, $i, $rd",
[(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>;
: F4_2<0b101100, (outs IntRegs:$rd),
(ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
"mov$cond %fcc0, $simm11, $rd",
[(set i32:$rd,
(SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
}
let Uses = [ICC] in {
let Uses = [ICC], opf_cc = 0b100 in {
def FMOVS_ICC
: Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
"fmovs$cc %icc, $rs2, $rd",
[(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>;
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
"fmovs$cond %icc, $rs2, $rd",
[(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
def FMOVD_ICC
: Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
"fmovd$cc %icc, $rs2, $rd",
[(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>;
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond %icc, $rs2, $rd",
[(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
def FMOVQ_ICC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovd$cond %icc, $rs2, $rd",
[(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
}
let Uses = [FCC] in {
let Uses = [FCC], opf_cc = 0b000 in {
def FMOVS_FCC
: Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
"fmovs$cc %fcc0, $rs2, $rd",
[(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>;
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
"fmovs$cond %fcc0, $rs2, $rd",
[(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
def FMOVD_FCC
: Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
"fmovd$cc %fcc0, $rs2, $rd",
[(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>;
: F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
"fmovd$cond %fcc0, $rs2, $rd",
[(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
def FMOVQ_FCC
: F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
"fmovd$cond %fcc0, $rs2, $rd",
[(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
}
}