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Add missing SSE builtins:
__builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -112,11 +112,18 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">,
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Intrinsic<[llvm_i32_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse_cvtss2si64 : GCCBuiltin<"__builtin_ia32_cvtss2si64">,
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Intrinsic<[llvm_i64_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
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Intrinsic<[llvm_i32_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse_cvttss2si64 : GCCBuiltin<"__builtin_ia32_cvttss2si64">,
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Intrinsic<[llvm_i64_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_sse_cvtsi642ss : GCCBuiltin<"__builtin_ia32_cvtsi642ss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_i64_ty], [IntrNoMem]>;
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}
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// SIMD load ops
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@ -387,11 +394,18 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v2f64_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,
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Intrinsic<[llvm_i32_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsd2si64 : GCCBuiltin<"__builtin_ia32_cvtsd2si64">,
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Intrinsic<[llvm_i64_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">,
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Intrinsic<[llvm_i32_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvttsd2si64 : GCCBuiltin<"__builtin_ia32_cvttsd2si64">,
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Intrinsic<[llvm_i64_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsi2sd : GCCBuiltin<"__builtin_ia32_cvtsi2sd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsi642sd : GCCBuiltin<"__builtin_ia32_cvtsi642sd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_i64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsd2ss : GCCBuiltin<"__builtin_ia32_cvtsd2ss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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@ -900,10 +900,12 @@ def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
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// f64 -> signed i64
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def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"cvtsd2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst,
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(int_x86_sse2_cvtsd2si64 VR128:$src))]>;
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def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
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"cvtsd2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst, (int_x86_sse2_cvtsd2si64
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(load addr:$src)))]>;
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def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
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"cvttsd2si{q} {$src, $dst|$dst, $src}",
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[(set GR64:$dst, (fp_to_sint FR64:$src))]>;
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@ -912,10 +914,13 @@ def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
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[(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
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def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"cvttsd2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst,
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(int_x86_sse2_cvttsd2si64 VR128:$src))]>;
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def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
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"cvttsd2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst,
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(int_x86_sse2_cvttsd2si64
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(load addr:$src)))]>;
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// Signed i64 -> f64
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def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
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@ -928,11 +933,15 @@ let isTwoAddress = 1 in {
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def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
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"cvtsi2sd{q} {$src2, $dst|$dst, $src2}",
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[]>; // TODO: add intrinsic
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[(set VR128:$dst,
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(int_x86_sse2_cvtsi642sd VR128:$src1,
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GR64:$src2))]>;
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def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
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"cvtsi2sd{q} {$src2, $dst|$dst, $src2}",
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[]>; // TODO: add intrinsic
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[(set VR128:$dst,
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(int_x86_sse2_cvtsi642sd VR128:$src1,
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(loadi64 addr:$src2)))]>;
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} // isTwoAddress
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// Signed i64 -> f32
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@ -956,10 +965,12 @@ def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem,
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// f32 -> signed i64
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def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"cvtss2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst,
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(int_x86_sse_cvtss2si64 VR128:$src))]>;
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def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
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"cvtss2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst, (int_x86_sse_cvtss2si64
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(load addr:$src)))]>;
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def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
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"cvttss2si{q} {$src, $dst|$dst, $src}",
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[(set GR64:$dst, (fp_to_sint FR32:$src))]>;
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@ -968,10 +979,27 @@ def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
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[(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
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def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"cvttss2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst,
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(int_x86_sse_cvttss2si64 VR128:$src))]>;
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def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
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"cvttss2si{q} {$src, $dst|$dst, $src}",
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[]>; // TODO: add intrinsic
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[(set GR64:$dst,
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(int_x86_sse_cvttss2si64 (load addr:$src)))]>;
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let isTwoAddress = 1 in {
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def Int_CVTSI642SSrr : RSSI<0x2A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
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"cvtsi2ss{q} {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(int_x86_sse_cvtsi642ss VR128:$src1,
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GR64:$src2))]>;
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def Int_CVTSI642SSrm : RSSI<0x2A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
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"cvtsi2ss{q} {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(int_x86_sse_cvtsi642ss VR128:$src1,
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(loadi64 addr:$src2)))]>;
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}
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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