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https://github.com/c64scene-ar/llvm-6502.git
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Various small changes related to the Condition Register on PowerPC.
Don't spill to the CR save area when using the SVR4 ABI for now. Don't rely on constants assigned for registers to be in order (they aren't assigned in order). Make sure CR bits are mapped to the corresponding CR field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74767 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller
parent
2a9ddfb903
commit
6a3a1ba97e
@ -139,21 +139,22 @@ public:
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std::pair<unsigned, int>(PPC::R14, -72),
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// CR save area offset.
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std::pair<unsigned, int>(PPC::CR2, -4),
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std::pair<unsigned, int>(PPC::CR3, -4),
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std::pair<unsigned, int>(PPC::CR4, -4),
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std::pair<unsigned, int>(PPC::CR2LT, -4),
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std::pair<unsigned, int>(PPC::CR2GT, -4),
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std::pair<unsigned, int>(PPC::CR2EQ, -4),
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std::pair<unsigned, int>(PPC::CR2UN, -4),
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std::pair<unsigned, int>(PPC::CR3LT, -4),
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std::pair<unsigned, int>(PPC::CR3GT, -4),
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std::pair<unsigned, int>(PPC::CR3EQ, -4),
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std::pair<unsigned, int>(PPC::CR3UN, -4),
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std::pair<unsigned, int>(PPC::CR4LT, -4),
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std::pair<unsigned, int>(PPC::CR4GT, -4),
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std::pair<unsigned, int>(PPC::CR4EQ, -4),
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std::pair<unsigned, int>(PPC::CR4UN, -4),
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// FIXME SVR4: Disable CR save area for now.
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// std::pair<unsigned, int>(PPC::CR2, -4),
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// std::pair<unsigned, int>(PPC::CR3, -4),
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// std::pair<unsigned, int>(PPC::CR4, -4),
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// std::pair<unsigned, int>(PPC::CR2LT, -4),
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// std::pair<unsigned, int>(PPC::CR2GT, -4),
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// std::pair<unsigned, int>(PPC::CR2EQ, -4),
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// std::pair<unsigned, int>(PPC::CR2UN, -4),
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// std::pair<unsigned, int>(PPC::CR3LT, -4),
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// std::pair<unsigned, int>(PPC::CR3GT, -4),
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// std::pair<unsigned, int>(PPC::CR3EQ, -4),
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// std::pair<unsigned, int>(PPC::CR3UN, -4),
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// std::pair<unsigned, int>(PPC::CR4LT, -4),
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// std::pair<unsigned, int>(PPC::CR4GT, -4),
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// std::pair<unsigned, int>(PPC::CR4EQ, -4),
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// std::pair<unsigned, int>(PPC::CR4UN, -4),
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// VRSAVE save area offset.
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std::pair<unsigned, int>(PPC::VRSAVE, -4),
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@ -444,21 +444,29 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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// not cause any bug. If we need other uses of CR bits, the following
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// code may be invalid.
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unsigned Reg = 0;
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if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
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if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
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SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
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Reg = PPC::CR0;
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else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
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else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
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SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
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Reg = PPC::CR1;
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else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
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else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
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SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
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Reg = PPC::CR2;
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else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
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else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
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SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
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Reg = PPC::CR3;
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else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
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else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
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SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
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Reg = PPC::CR4;
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else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
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else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
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SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
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Reg = PPC::CR5;
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else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
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else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
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SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
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Reg = PPC::CR6;
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else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
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else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
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SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
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Reg = PPC::CR7;
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return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
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@ -587,21 +595,29 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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} else if (RC == PPC::CRBITRCRegisterClass) {
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unsigned Reg = 0;
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if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
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if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
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DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
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Reg = PPC::CR0;
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else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
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else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
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DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
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Reg = PPC::CR1;
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else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
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else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
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DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
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Reg = PPC::CR2;
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else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
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else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
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DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
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Reg = PPC::CR3;
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else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
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else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
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DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
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Reg = PPC::CR4;
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else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
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else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
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DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
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Reg = PPC::CR5;
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else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
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else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
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DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
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Reg = PPC::CR6;
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else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
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else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
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DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
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Reg = PPC::CR7;
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return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
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@ -1049,9 +1049,10 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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if (Reg < MinFPR) {
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MinFPR = Reg;
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}
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} else if ( RC == PPC::CRBITRCRegisterClass
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// FIXME SVR4: Disable CR save area for now.
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} else if ( RC == PPC::CRBITRCRegisterClass
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|| RC == PPC::CRRCRegisterClass) {
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HasCRSaveArea = true;
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// HasCRSaveArea = true;
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} else if (RC == PPC::VRSAVERCRegisterClass) {
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HasVRSAVESaveArea = true;
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} else if (RC == PPC::VRRCRegisterClass) {
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@ -43,8 +43,9 @@ class VR<bits<5> num, string n> : PPCReg<n> {
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}
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// CR - One of the 8 4-bit condition registers
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class CR<bits<3> num, string n> : PPCReg<n> {
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class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
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field bits<3> Num = num;
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let SubRegs = subregs;
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}
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// CRBIT - One of the 32 1-bit condition register fields
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@ -189,16 +190,6 @@ def V29 : VR<29, "v29">, DwarfRegNum<[106]>;
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def V30 : VR<30, "v30">, DwarfRegNum<[107]>;
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def V31 : VR<31, "v31">, DwarfRegNum<[108]>;
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// Condition registers
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def CR0 : CR<0, "cr0">, DwarfRegNum<[68]>;
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def CR1 : CR<1, "cr1">, DwarfRegNum<[69]>;
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def CR2 : CR<2, "cr2">, DwarfRegNum<[70]>;
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def CR3 : CR<3, "cr3">, DwarfRegNum<[71]>;
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def CR4 : CR<4, "cr4">, DwarfRegNum<[72]>;
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def CR5 : CR<5, "cr5">, DwarfRegNum<[73]>;
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def CR6 : CR<6, "cr6">, DwarfRegNum<[74]>;
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def CR7 : CR<7, "cr7">, DwarfRegNum<[75]>;
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// Condition register bits
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def CR0LT : CRBIT< 0, "0">, DwarfRegNum<[0]>;
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def CR0GT : CRBIT< 1, "1">, DwarfRegNum<[0]>;
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@ -233,6 +224,16 @@ def CR7GT : CRBIT<29, "29">, DwarfRegNum<[0]>;
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def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>;
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def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>;
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// Condition registers
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def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>;
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def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>;
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def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>;
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def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71]>;
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def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>;
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def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>;
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def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>;
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def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>;
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def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
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[CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
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def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
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@ -348,9 +349,6 @@ def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
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V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
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V29, V28, V27, V26, V25, V24, V23, V22, V21, V20]>;
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def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
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CR3, CR4]>;
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def CRBITRC : RegisterClass<"PPC", [i32], 32,
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[CR0LT, CR0GT, CR0EQ, CR0UN,
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CR1LT, CR1GT, CR1EQ, CR1UN,
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@ -365,6 +363,11 @@ def CRBITRC : RegisterClass<"PPC", [i32], 32,
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let CopyCost = -1;
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}
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def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
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CR3, CR4]>
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{
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let SubRegClassList = [CRBITRC, CRBITRC, CRBITRC, CRBITRC];
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}
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def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>;
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def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>;
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