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Add mcr*2 and mr*c2 support to thumb2 targets

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-01-20 16:58:48 +00:00
parent fa5bd27fbe
commit 6b3a999f22
3 changed files with 75 additions and 0 deletions
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6
lib/Target/ARM/ARMInstrFormats.td
View File

@ -1054,6 +1054,12 @@ class T2JTI<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
// Move to/from coprocessor instructions
class T2Cop<dag oops, dag iops, string asm, list<dag> pattern>
: T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> {
let Inst{31-28} = 0b1111;
}
// Two-address instructions
class T2XIt<dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>

56
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3322,3 +3322,59 @@ def t2MSRsys : T2MSR<0b111100111001, 0b10, 0,
(outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
"\tspsr$mask, $Rn",
[/* For disassembly only; pattern left blank */]>;
//===----------------------------------------------------------------------===//
// Move between coprocessor and ARM core register -- for disassembly only
//
class t2MovRCopro<string opc, bit direction>
: T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1110;
let Inst{20} = direction;
let Inst{4} = 1;
bits<4> Rt;
bits<4> cop;
bits<3> opc1;
bits<3> opc2;
bits<4> CRm;
bits<4> CRn;
let Inst{15-12} = Rt;
let Inst{11-8} = cop;
let Inst{23-21} = opc1;
let Inst{7-5} = opc2;
let Inst{3-0} = CRm;
let Inst{19-16} = CRn;
}
def t2MCR : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */>;
def t2MRC : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */>;
class t2MovRRCopro<string opc, bit direction>
: T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1100;
let Inst{23-21} = 0b010;
let Inst{20} = direction;
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
bits<4> opc1;
bits<4> CRm;
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
let Inst{7-4} = opc1;
let Inst{3-0} = CRm;
}
def t2MCRR : t2MovRRCopro<"mcrr2",0/* from ARM core register to coprocessor */>;
def t2MRRC : t2MovRRCopro<"mrrc2",1/* from coprocessor to ARM core register */>;

13
test/MC/ARM/thumb2.s
View File

@ -181,3 +181,16 @@
vmsr fpexc, r0
@ CHECK: vmsr fpsid, r0 @ encoding: [0xe0,0xee,0x10,0x0a]
vmsr fpsid, r0
@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57]
mcr2 p7, #1, r5, c1, c1, #4
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
mrc2 p14, #0, r1, c1, c2, #4
@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x44,0xfc,0x11,0x57]
mcrr2 p7, #1, r5, r4, c1
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57]
mrrc2 p7, #1, r5, r4, c1