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R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP
This is only a workaround. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223615 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -41,6 +41,12 @@ typedef union {
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} Counters;
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typedef enum {
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OTHER,
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SMEM,
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VMEM
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} InstType;
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typedef Counters RegCounters[512];
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typedef std::pair<unsigned, unsigned> RegInterval;
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@ -73,6 +79,9 @@ private:
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/// \brief Different export instruction types seen since last wait.
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unsigned ExpInstrTypesSeen;
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/// \brief Type of the last opcode.
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InstType LastOpcodeType;
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/// \brief Get increment/decrement amount for this instruction.
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Counters getHwCounts(MachineInstr &MI);
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@ -83,7 +92,8 @@ private:
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RegInterval getRegInterval(MachineOperand &Op);
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/// \brief Handle instructions async components
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void pushInstruction(MachineInstr &MI);
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void pushInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I);
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/// \brief Insert the actual wait instruction
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bool insertWait(MachineBasicBlock &MBB,
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@ -203,10 +213,11 @@ RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
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return Result;
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}
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void SIInsertWaits::pushInstruction(MachineInstr &MI) {
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void SIInsertWaits::pushInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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// Get the hardware counter increments and sum them up
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Counters Increment = getHwCounts(MI);
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Counters Increment = getHwCounts(*I);
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unsigned Sum = 0;
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for (unsigned i = 0; i < 3; ++i) {
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@ -215,17 +226,42 @@ void SIInsertWaits::pushInstruction(MachineInstr &MI) {
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}
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// If we don't increase anything then that's it
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if (Sum == 0)
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if (Sum == 0) {
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LastOpcodeType = OTHER;
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return;
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}
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if (TRI->ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
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// Any occurence of consecutive VMEM or SMEM instructions forms a VMEM
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// or SMEM clause, respectively.
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//
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// The temporary workaround is to break the clauses with S_NOP.
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//
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// The proper solution would be to allocate registers such that all source
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// and destination registers don't overlap, e.g. this is illegal:
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// r0 = load r2
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// r2 = load r0
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if ((LastOpcodeType == SMEM && TII->isSMRD(I->getOpcode())) ||
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(LastOpcodeType == VMEM && Increment.Named.VM)) {
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// Insert a NOP to break the clause.
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BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP))
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.addImm(0);
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}
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if (TII->isSMRD(I->getOpcode()))
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LastOpcodeType = SMEM;
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else if (Increment.Named.VM)
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LastOpcodeType = VMEM;
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}
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// Remember which export instructions we have seen
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if (Increment.Named.EXP) {
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ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
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ExpInstrTypesSeen |= I->getOpcode() == AMDGPU::EXP ? 1 : 2;
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}
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &Op = MI.getOperand(i);
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MachineOperand &Op = I->getOperand(i);
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if (!isOpRelevant(Op))
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continue;
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@ -302,6 +338,7 @@ bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
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((Counts.Named.EXP & 0x7) << 4) |
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((Counts.Named.LGKM & 0x7) << 8));
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LastOpcodeType = OTHER;
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return true;
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}
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@ -356,6 +393,7 @@ bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
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WaitedOn = ZeroCounts;
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LastIssued = ZeroCounts;
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LastOpcodeType = OTHER;
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memset(&UsedRegs, 0, sizeof(UsedRegs));
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memset(&DefinedRegs, 0, sizeof(DefinedRegs));
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@ -368,7 +406,7 @@ bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
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I != E; ++I) {
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Changes |= insertWait(MBB, I, handleOperands(*I));
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pushInstruction(*I);
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pushInstruction(MBB, I);
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}
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// Wait for everything at the end of the MBB
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