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Add a FIXME. The ADR instruction is a bit odd.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-13 21:32:30 +00:00
parent b3af5de2d9
commit 6c354fd3f5
1 changed files with 6 additions and 2 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
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@ -936,8 +936,9 @@ def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV7]> {
let Inst{27-16} = 0b001100100000;
let Inst{7-4} = 0b1111;
bits<4> opt;
let Inst{27-4} = 0b001100100000111100001111;
let Inst{3-0} = opt;
}
// A5.4 Permanently UNDEFINED instructions.
@ -996,6 +997,9 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
// FIXME: These are marked as pseudos, but they're really not(?). They're just
// the ADR instruction. Is this the right way to handle that? They need
// encoding information regardless.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),