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Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern

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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-13 21:00:04 +00:00
parent 67a704de03
commit b3af5de2d9
7 changed files with 33 additions and 19 deletions
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3
lib/Target/ARM/ARMInstrFormats.td
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@ -165,6 +165,9 @@ def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
// ARM special operands for disassembly only.
//
def setend_op : Operand<i32> {
let PrintMethod = "printSetendOperand";
}
def cps_opt : Operand<i32> {
let PrintMethod = "printCPSOptionOperand";

24
lib/Target/ARM/ARMInstrInfo.td
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@ -923,24 +923,14 @@ defm PLD : APreLoad<1, 1, "pld">;
defm PLDW : APreLoad<1, 0, "pldw">;
defm PLI : APreLoad<0, 1, "pli">;
def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
[/* For disassembly only; pattern left blank */]>,
def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
"setend\t$end",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM]> {
let Inst{31-28} = 0b1111;
let Inst{27-20} = 0b00010000;
let Inst{16} = 1;
let Inst{9} = 1;
let Inst{7-4} = 0b0000;
}
def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM]> {
let Inst{31-28} = 0b1111;
let Inst{27-20} = 0b00010000;
let Inst{16} = 1;
let Inst{9} = 0;
let Inst{7-4} = 0b0000;
bits<1> end;
let Inst{31-10} = 0b1111000100000001000000;
let Inst{9} = end;
let Inst{8-0} = 0;
}
def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",

8
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -2998,13 +2998,17 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
case ARM::WFE:
case ARM::WFI:
case ARM::SEV:
case ARM::SETENDBE:
case ARM::SETENDLE:
return true;
default:
break;
}
if (Opcode == ARM::SETEND) {
NumOpsAdded = 1;
MI.addOperand(MCOperand::CreateImm(slice(insn, 9, 9)));
return true;
}
// CPS has a singleton $opt operand that contains the following information:
// opt{4-0} = mode from Inst{4-0}
// opt{5} = changemode from Inst{17}

9
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@ -400,6 +400,15 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
O << "}";
}
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNum);
if (Op.getImm())
O << "be";
else
O << "le";
}
void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNum);

1
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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@ -87,6 +87,7 @@ public:
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

6
test/MC/Disassembler/arm-tests.txt
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@ -109,3 +109,9 @@
# CHECK: usat r8, #0, r10, asr #32
0x5a 0x80 0xe0 0xe6
# CHECK: setend be
0x00 0x02 0x01 0xf1
# CHECK: setend le
0x00 0x00 0x01 0xf1

1
utils/TableGen/EDEmitter.cpp
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@ -567,6 +567,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("jtblock_operand");
IMM("nohash_imm");
IMM("cpinst_operand");
IMM("setend_op");
IMM("cps_opt");
IMM("vfp_f64imm");
IMM("vfp_f32imm");