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Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163298 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy
parent
7859f438e1
commit
6c822eea47
@ -1208,6 +1208,57 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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ExpandLaneOp(MBBI);
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return true;
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case ARM::VSETLNi8Q:
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case ARM::VSETLNi16Q: {
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// Expand VSETLNs acting on a Q register to equivalent VSETLNs acting
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// on the respective D register.
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unsigned QReg = MI.getOperand(1).getReg();
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unsigned QLane = MI.getOperand(3).getImm();
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unsigned NewOpcode, DLane, DSubReg;
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switch (Opcode) {
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default: llvm_unreachable("Invalid opcode!");
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case ARM::VSETLNi8Q:
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// 4 possible 8-bit lanes per DPR:
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NewOpcode = ARM::VSETLNi8;
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DLane = QLane % 8;
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DSubReg = (QLane / 8) ? ARM::dsub_1 : ARM::dsub_0;
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break;
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case ARM::VSETLNi16Q:
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// 4 possible 16-bit lanes per DPR.
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NewOpcode = ARM::VSETLNi16;
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DLane = QLane % 4;
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DSubReg = (QLane / 4) ? ARM::dsub_1 : ARM::dsub_0;
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break;
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}
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpcode));
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unsigned DReg = TRI->getSubReg(QReg, DSubReg);
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MIB.addReg(DReg, RegState::Define); // Output DPR
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MIB.addReg(DReg); // Input DPR
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MIB.addOperand(MI.getOperand(2)); // Input GPR
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MIB.addImm(DLane); // Lane
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// Add the predicate operands.
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MIB.addOperand(MI.getOperand(4));
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MIB.addOperand(MI.getOperand(5));
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if (MI.getOperand(1).isKill()) // Add an implicit kill for the Q register.
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MIB->addRegisterKilled(QReg, TRI, true);
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// And an implicit def of the output register (which should always be the
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// same as the input register).
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MIB->addRegisterDefined(QReg, TRI);
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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return true;
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}
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case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
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case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
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case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
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@ -5045,25 +5045,23 @@ def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
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GPR:$R, imm:$lane))]> {
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let Inst{21} = lane{0};
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}
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def VSETLNi8Q : PseudoNeonI<(outs QPR:$V),
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(ins QPR:$src1, GPR:$R, VectorIndex8:$lane),
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IIC_VMOVISL, "",
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[(set QPR:$V, (vector_insert (v16i8 QPR:$src1),
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GPR:$R, imm:$lane))]>;
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def VSETLNi16Q : PseudoNeonI<(outs QPR:$V),
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(ins QPR:$src1, GPR:$R, VectorIndex16:$lane),
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IIC_VMOVISL, "",
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[(set QPR:$V, (vector_insert (v8i16 QPR:$src1),
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GPR:$R, imm:$lane))]>;
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}
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def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
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(v16i8 (INSERT_SUBREG QPR:$src1,
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(v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
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(DSubReg_i8_reg imm:$lane))),
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GPR:$src2, (SubReg_i8_lane imm:$lane))),
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(DSubReg_i8_reg imm:$lane)))>;
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def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
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(v8i16 (INSERT_SUBREG QPR:$src1,
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(v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
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(DSubReg_i16_reg imm:$lane))),
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GPR:$src2, (SubReg_i16_lane imm:$lane))),
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(DSubReg_i16_reg imm:$lane)))>;
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def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
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(v4i32 (INSERT_SUBREG QPR:$src1,
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(v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
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(DSubReg_i32_reg imm:$lane))),
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GPR:$src2, (SubReg_i32_lane imm:$lane))),
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(DSubReg_i32_reg imm:$lane)))>;
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(v4i32 (INSERT_SUBREG QPR:$src1,
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GPR:$src2,
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(SSubReg_f32_reg imm:$lane)))>;
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def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
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(INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
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35
test/CodeGen/ARM/integer_insertelement.ll
Normal file
35
test/CodeGen/ARM/integer_insertelement.ll
Normal file
@ -0,0 +1,35 @@
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; RUN: llc %s -o - -march=arm -mattr=+neon | FileCheck %s
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; This test checks that when inserting one (integer) element into a vector,
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; the vector is not spuriously copied. "vorr dX, dY, dY" is the way of moving
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; one DPR to another that we check for.
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; CHECK: @f
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; CHECK-NOT: vorr d
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; CHECK: vmov s
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; CHECK-NOT: vorr d
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; CHECK: mov pc, lr
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define <4 x i32> @f(<4 x i32> %in) {
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%1 = insertelement <4 x i32> %in, i32 255, i32 3
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ret <4 x i32> %1
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}
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; CHECK: @g
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; CHECK-NOT: vorr d
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; CHECK: vmov.16 d
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; CHECK-NOT: vorr d
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; CHECK: mov pc, lr
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define <8 x i16> @g(<8 x i16> %in) {
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%1 = insertelement <8 x i16> %in, i16 255, i32 7
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ret <8 x i16> %1
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}
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; CHECK: @h
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; CHECK-NOT: vorr d
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; CHECK: vmov.8 d
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; CHECK-NOT: vorr d
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; CHECK: mov pc, lr
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define <16 x i8> @h(<16 x i8> %in) {
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%1 = insertelement <16 x i8> %in, i8 255, i32 15
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ret <16 x i8> %1
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}
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@ -200,7 +200,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
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define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
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;CHECK: vsetQ_lane32:
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;CHECK: vmov.32
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;CHECK: vmov s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
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ret <4 x i32> %tmp2
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