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Implement vector expand support for shuffle_vector. This fixes PR1811.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44242 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6286,6 +6286,41 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
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TLI.getPointerTy()));
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break;
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}
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case ISD::VECTOR_SHUFFLE: {
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// Build the low part.
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SDOperand Mask = Node->getOperand(2);
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SmallVector<SDOperand, 8> Ops;
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MVT::ValueType PtrVT = TLI.getPointerTy();
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// Insert all of the elements from the input that are needed. We use
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// buildvector of extractelement here because the input vectors will have
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// to be legalized, so this makes the code simpler.
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for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
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unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
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SDOperand InVec = Node->getOperand(0);
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if (Idx >= NumElements) {
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InVec = Node->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
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DAG.getConstant(Idx, PtrVT)));
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}
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Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
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Ops.clear();
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for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
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unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
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SDOperand InVec = Node->getOperand(0);
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if (Idx >= NumElements) {
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InVec = Node->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
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DAG.getConstant(Idx, PtrVT)));
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}
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Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
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break;
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}
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case ISD::BUILD_VECTOR: {
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SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
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Node->op_begin()+NewNumElts_Lo);
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