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Don't use MachineOperator::is(Phys|Virt)Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11276 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
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}
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static unsigned getFPReg(const MachineOperand &MO) {
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assert(MO.isPhysicalRegister() && "Expected an FP register!");
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assert(MO.isRegister() && "Expected an FP register!");
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unsigned Reg = MO.getReg();
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assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
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return Reg - X86::FP0;
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@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
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}
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static unsigned getFPReg(const MachineOperand &MO) {
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assert(MO.isPhysicalRegister() && "Expected an FP register!");
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assert(MO.isRegister() && "Expected an FP register!");
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unsigned Reg = MO.getReg();
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assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
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return Reg - X86::FP0;
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@ -42,8 +42,8 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `xchg ax, ax'
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if (MI.getOpcode() == X86::XCHGrr16) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isPhysicalRegister() && op0.getReg() == X86::AX &&
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op1.isPhysicalRegister() && op1.getReg() == X86::AX) {
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if (op0.isRegister() && op0.getReg() == X86::AX &&
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op1.isRegister() && op1.getReg() == X86::AX) {
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return true;
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}
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}
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