mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Implement optimization folding setcc into branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5324 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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b037ee822c
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@ -151,14 +151,9 @@ namespace {
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void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
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void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
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// Binary comparison operators
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void visitSetCCInst(SetCondInst &I, unsigned OpNum);
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void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
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void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
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void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
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void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
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void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
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void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
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// Comparison operators...
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void visitSetCondInst(SetCondInst &I);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
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// Memory Instructions
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MachineInstr *doFPLoad(MachineBasicBlock *MBB,
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@ -482,31 +477,59 @@ void ISel::SelectPHINodes() {
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}
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}
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// canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
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// the conditional branch instruction which is the only user of the cc
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// instruction. This is the case if the conditional branch is the only user of
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// the setcc, and if the setcc is in the same basic block as the conditional
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// branch. We also don't handle long arguments below, so we reject them here as
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// well.
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//
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static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
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if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
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if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
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SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
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const Type *Ty = SCI->getOperand(0)->getType();
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if (Ty != Type::LongTy && Ty != Type::ULongTy)
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return SCI;
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}
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return 0;
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}
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// Return a fixed numbering for setcc instructions which does not depend on the
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// order of the opcodes.
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//
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static unsigned getSetCCNumber(unsigned Opcode) {
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switch(Opcode) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: return 0;
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case Instruction::SetNE: return 1;
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case Instruction::SetLT: return 2;
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case Instruction::SetGT: return 3;
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case Instruction::SetLE: return 4;
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case Instruction::SetGE: return 5;
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}
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}
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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static const unsigned SetCCOpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
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};
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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///
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void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = I.getOperand(0)->getType();
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const Type *CompTy = Op0->getType();
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bool isSigned = CompTy->isSigned();
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unsigned reg1 = getReg(I.getOperand(0));
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unsigned reg2 = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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static const unsigned OpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
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};
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unsigned reg1 = getReg(Op0);
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unsigned reg2 = getReg(Op1);
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unsigned Class = getClassB(CompTy);
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switch (Class) {
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@ -549,21 +572,43 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// dest = hi(op1) == hi(op2) ? AL : BL;
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//
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// FIXME: This would be much better if we had heirarchical register
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// FIXME: This would be much better if we had hierarchical register
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// classes! Until then, hardcode registers so that we can deal with their
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// aliases (because we don't have conditional byte moves).
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//
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BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
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BuildMI(BB, OpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 0, X86::BL);
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
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return;
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// NOTE: visitSetCondInst knows that the value is dumped into the BL
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// register at this point for long values...
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return isSigned;
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}
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}
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return isSigned;
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}
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 0, DestReg);
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
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unsigned OpNum = getSetCCNumber(I.getOpcode());
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unsigned DestReg = getReg(I);
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bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
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I.getOperand(1));
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if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
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// Handle normal comparisons with a setcc instruction...
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
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} else {
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// Handle long comparisons by copying the value which is already in BL into
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// the register we want...
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BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
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}
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}
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/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
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@ -636,15 +681,45 @@ void ISel::visitReturnInst(ReturnInst &I) {
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/// visitBranchInst - Handle conditional and unconditional branches here. Note
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/// that since code layout is frozen at this point, that if we are trying to
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/// jump to a block that is the immediate successor of the current block, we can
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/// just make a fall-through. (but we don't currently).
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/// just make a fall-through (but we don't currently).
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///
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void ISel::visitBranchInst(BranchInst &BI) {
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if (BI.isConditional()) {
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if (!BI.isConditional()) {
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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return;
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}
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// See if we can fold the setcc into the branch itself...
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SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
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if (SCI == 0) {
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// Nope, cannot fold setcc into this branch. Emit a branch on a condition
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// computed some other way...
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unsigned condReg = getReg(BI.getCondition());
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BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
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BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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return;
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}
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
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SCI->getOperand(1));
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> je je
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// setne -> jne jne
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// setlt -> jl jb
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// setgt -> jg ja
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// setle -> jle jbe
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// setge -> jge jae
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static const unsigned OpcodeTab[2][6] = {
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{ X86::JE, X86::JNE, X86::JB, X86::JA, X86::JBE, X86::JAE },
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{ X86::JE, X86::JNE, X86::JL, X86::JG, X86::JLE, X86::JGE },
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};
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
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}
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@ -151,14 +151,9 @@ namespace {
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void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
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void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
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// Binary comparison operators
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void visitSetCCInst(SetCondInst &I, unsigned OpNum);
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void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
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void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
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void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
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void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
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void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
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void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
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// Comparison operators...
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void visitSetCondInst(SetCondInst &I);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
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// Memory Instructions
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MachineInstr *doFPLoad(MachineBasicBlock *MBB,
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@ -482,31 +477,59 @@ void ISel::SelectPHINodes() {
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}
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}
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// canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
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// the conditional branch instruction which is the only user of the cc
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// instruction. This is the case if the conditional branch is the only user of
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// the setcc, and if the setcc is in the same basic block as the conditional
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// branch. We also don't handle long arguments below, so we reject them here as
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// well.
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//
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static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
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if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
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if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
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SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
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const Type *Ty = SCI->getOperand(0)->getType();
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if (Ty != Type::LongTy && Ty != Type::ULongTy)
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return SCI;
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}
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return 0;
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}
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// Return a fixed numbering for setcc instructions which does not depend on the
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// order of the opcodes.
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//
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static unsigned getSetCCNumber(unsigned Opcode) {
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switch(Opcode) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: return 0;
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case Instruction::SetNE: return 1;
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case Instruction::SetLT: return 2;
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case Instruction::SetGT: return 3;
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case Instruction::SetLE: return 4;
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case Instruction::SetGE: return 5;
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}
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}
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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static const unsigned SetCCOpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
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};
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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///
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void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = I.getOperand(0)->getType();
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const Type *CompTy = Op0->getType();
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bool isSigned = CompTy->isSigned();
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unsigned reg1 = getReg(I.getOperand(0));
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unsigned reg2 = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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static const unsigned OpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
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};
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unsigned reg1 = getReg(Op0);
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unsigned reg2 = getReg(Op1);
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unsigned Class = getClassB(CompTy);
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switch (Class) {
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@ -549,21 +572,43 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// dest = hi(op1) == hi(op2) ? AL : BL;
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//
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// FIXME: This would be much better if we had heirarchical register
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// FIXME: This would be much better if we had hierarchical register
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// classes! Until then, hardcode registers so that we can deal with their
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// aliases (because we don't have conditional byte moves).
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//
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BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
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BuildMI(BB, OpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 0, X86::BL);
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
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return;
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// NOTE: visitSetCondInst knows that the value is dumped into the BL
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// register at this point for long values...
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return isSigned;
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}
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}
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return isSigned;
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}
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 0, DestReg);
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
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unsigned OpNum = getSetCCNumber(I.getOpcode());
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unsigned DestReg = getReg(I);
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bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
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I.getOperand(1));
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if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
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// Handle normal comparisons with a setcc instruction...
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BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
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} else {
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// Handle long comparisons by copying the value which is already in BL into
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// the register we want...
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BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
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}
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}
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/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
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@ -636,15 +681,45 @@ void ISel::visitReturnInst(ReturnInst &I) {
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/// visitBranchInst - Handle conditional and unconditional branches here. Note
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/// that since code layout is frozen at this point, that if we are trying to
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/// jump to a block that is the immediate successor of the current block, we can
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/// just make a fall-through. (but we don't currently).
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/// just make a fall-through (but we don't currently).
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///
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void ISel::visitBranchInst(BranchInst &BI) {
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if (BI.isConditional()) {
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if (!BI.isConditional()) {
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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return;
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}
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// See if we can fold the setcc into the branch itself...
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SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
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if (SCI == 0) {
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// Nope, cannot fold setcc into this branch. Emit a branch on a condition
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// computed some other way...
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unsigned condReg = getReg(BI.getCondition());
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BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
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BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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return;
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}
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
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SCI->getOperand(1));
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> je je
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// setne -> jne jne
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// setlt -> jl jb
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// setgt -> jg ja
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// setle -> jle jbe
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// setge -> jge jae
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static const unsigned OpcodeTab[2][6] = {
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{ X86::JE, X86::JNE, X86::JB, X86::JA, X86::JBE, X86::JAE },
|
||||
{ X86::JE, X86::JNE, X86::JL, X86::JG, X86::JLE, X86::JGE },
|
||||
};
|
||||
|
||||
BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
|
||||
BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
|
||||
}
|
||||
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user