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Add ARMv7 architecture, Cortex processors and different FPU modes handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -28,8 +28,14 @@ def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
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"ARM v5TE, v5TEj, v5TExp">;
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def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
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"ARM v6">;
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFP2", "true",
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A">;
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def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
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"Enable VFP2 instructions ">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
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"Enable VFP3 instructions ">;
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def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
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"Enable NEON instructions ">;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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@ -84,6 +90,9 @@ def : Proc<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
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def : Proc<"mpcorenovfp", [ArchV6]>;
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def : Proc<"mpcore", [ArchV6, FeatureVFP2]>;
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def : Proc<"cortex-a8", [ArchV7A, FeatureNEON]>;
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def : Proc<"cortex-a9", [ArchV7A, FeatureNEON]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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@ -18,7 +18,7 @@ using namespace llvm;
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ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS, bool thumb)
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: ARMArchVersion(V4T)
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, HasVFP2(false)
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, ARMFPUType(None)
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, IsThumb(thumb)
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, UseThumbBacktraces(false)
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, IsR9Reserved(false)
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@ -23,16 +23,19 @@ class Module;
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class ARMSubtarget : public TargetSubtarget {
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protected:
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enum ARMArchEnum {
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V4T, V5T, V5TE, V6
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V4T, V5T, V5TE, V6, V7A
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};
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/// ARMArchVersion - ARM architecture vecrsion: V4T (base), V5T, V5TE,
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/// and V6.
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enum ARMFPEnum {
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None, VFPv2, VFPv3, NEON
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};
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/// ARMArchVersion - ARM architecture version: V4T (base), V5T, V5TE,
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/// V6, V7A.
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ARMArchEnum ARMArchVersion;
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/// HasVFP2 - True if the processor supports Vector Floating Point (VFP) V2
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/// instructions.
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bool HasVFP2;
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/// ARMFPUType - Floating Point Unit type.
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ARMFPEnum ARMFPUType;
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/// IsThumb - True if we are in thumb mode, false if in ARM mode.
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bool IsThumb;
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@ -72,17 +75,20 @@ protected:
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// Change this once Thumb ldmia / stmia support is added.
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return isThumb() ? 0 : 64;
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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std::string ParseSubtargetFeatures(const std::string &FS,
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const std::string &CPU);
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bool hasV4TOps() const { return ARMArchVersion >= V4T; }
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bool hasV5TOps() const { return ARMArchVersion >= V5T; }
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bool hasV4TOps() const { return ARMArchVersion >= V4T; }
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bool hasV5TOps() const { return ARMArchVersion >= V5T; }
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bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
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bool hasV6Ops() const { return ARMArchVersion >= V6; }
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bool hasV6Ops() const { return ARMArchVersion >= V6; }
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bool hasV7Ops() const { return ARMArchVersion >= V7A; }
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bool hasVFP2() const { return HasVFP2; }
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bool hasVFP2() const { return ARMFPUType >= VFPv2; }
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bool hasVFP3() const { return ARMFPUType >= VFPv3; }
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bool hasNEON() const { return ARMFPUType >= NEON; }
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bool isTargetDarwin() const { return TargetType == isDarwin; }
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bool isTargetELF() const { return TargetType == isELF; }
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