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Split RegisterAllocation stuff OUT of Sparc.cpp into a well defined pass

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that has a very minimal interface (like it should have).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-02-04 00:33:08 +00:00
parent 7327d7ee8b
commit 6dd98a6c31
4 changed files with 60 additions and 31 deletions
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24
include/llvm/CodeGen/RegisterAllocation.h Normal file
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@ -0,0 +1,24 @@
//===-- CodeGen/RegisterAllocation.h - RegAlloc Pass -------------*- C++ -*--=//
//
// This pass register allocates a module, a method at a time.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_REGISTERALLOCATION_H
#define LLVM_CODEGEN_REGISTERALLOCATION_H
#include "llvm/Pass.h"
class TargetMachine;
//----------------------------------------------------------------------------
// Entry point for register allocation for a module
//----------------------------------------------------------------------------
class RegisterAllocation : public MethodPass {
TargetMachine &Target;
public:
inline RegisterAllocation(TargetMachine &T) : Target(T) {}
bool runOnMethod(Method *M);
};
#endif

19
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
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@ -10,6 +10,7 @@
// 9/10/01 - Ruchira Sasanka - created.
//**************************************************************************/
#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
@ -23,8 +24,6 @@ using std::cerr;
// ***TODO: There are several places we add instructions. Validate the order
// of adding these instructions.
cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
"enable register allocation debugging information",
clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
@ -32,6 +31,22 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
bool RegisterAllocation::runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
MethodLiveVarInfo LVI(M ); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.
//----------------------------------------------------------------------------

19
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
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@ -10,6 +10,7 @@
// 9/10/01 - Ruchira Sasanka - created.
//**************************************************************************/
#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
@ -23,8 +24,6 @@ using std::cerr;
// ***TODO: There are several places we add instructions. Validate the order
// of adding these instructions.
cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
"enable register allocation debugging information",
clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
@ -32,6 +31,22 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
bool RegisterAllocation::runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
MethodLiveVarInfo LVI(M ); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.
//----------------------------------------------------------------------------

29
lib/Target/SparcV9/SparcV9TargetMachine.cpp
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@ -16,7 +16,7 @@
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/Method.h"
#include "llvm/PassManager.h"
#include <iostream>
@ -40,32 +40,6 @@ const MachineInstrDescriptor SparcMachineInstrDesc[] = {
TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
//----------------------------------------------------------------------------
// Entry point for register allocation for a module
//----------------------------------------------------------------------------
class RegisterAllocation : public MethodPass {
TargetMachine &Target;
public:
inline RegisterAllocation(TargetMachine &T) : Target(T) {}
bool runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
MethodLiveVarInfo LVI(M ); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
}
};
static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
//---------------------------------------------------------------------------
// class InsertPrologEpilogCode
//
@ -77,6 +51,7 @@ static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
// with the leaf method optimization.
//
//---------------------------------------------------------------------------
static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
class InsertPrologEpilogCode : public MethodPass {
TargetMachine &Target;