6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 04:29:21 +00:00
Code Issues Projects Releases Wiki Activity

fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is

Browse Source 
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.

fixes multisource/obsequi (maybe others)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21075 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-04-04 05:05:52 +00:00
parent 09c61b9c19
commit 6e02e6842a
1 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/IA64/IA64ISelPattern.cpp
View File

@ -1087,9 +1087,19 @@ pC = pA OR pB
.addReg(TmpF8).addReg(TmpF10).addReg(TmpF10).addReg(TmpPR);
BuildMI(BB, IA64::CFNMAS1, 4,TmpF13)
.addReg(TmpF4).addReg(TmpF11).addReg(TmpF3).addReg(TmpPR);
// FIXME: this is unfortunate :(
// the story is that the dest reg of the fnma above and the fma below
// (and therefore possibly the src of the fcvt.fx[u] as well) cannot
// be the same register, or this code breaks if the first argument is
// zero. (e.g. without this hack, 0%8 yields -64, not 0.)
BuildMI(BB, IA64::CFMAS1, 4,TmpF14)
.addReg(TmpF13).addReg(TmpF12).addReg(TmpF11).addReg(TmpPR);
if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
BuildMI(BB, IA64::IUSE, 1).addReg(TmpF13); // hack :(
}
if(!isFP) {
// round to an integer
if(isSigned)
@ -1113,14 +1123,16 @@ pC = pA OR pB
BuildMI(BB, IA64::CFMOV, 2, Result)
.addReg(bogoResult).addReg(TmpF15).addReg(TmpPR);
}
else
else {
BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TmpF15);
}
} else { // this is a modulus
if(!isFP) {
// answer = q * (-b) + a
unsigned ModulusResult = MakeReg(MVT::f64);
unsigned TmpF = MakeReg(MVT::f64);
unsigned TmpI = MakeReg(MVT::i64);
BuildMI(BB, IA64::SUB, 2, TmpI).addReg(IA64::r0).addReg(Tmp2);
BuildMI(BB, IA64::SETFSIG, 1, TmpF).addReg(TmpI);
BuildMI(BB, IA64::XMAL, 3, ModulusResult)