6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 19:55:11 +00:00
Code Issues Projects Releases Wiki Activity

cleanup

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-06-02 13:53:17 +00:00
parent ce48c1de82
commit 6f07bd6ae8
22 changed files with 0 additions and 352 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -74,20 +74,6 @@ const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
};
return CalleeSavedRegClasses;
}
BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(Alpha::R15);

3
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -30,9 +30,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const TargetRegisterClass* const* getCalleeSavedRegClasses(
const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;

11
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@ -48,17 +48,6 @@ BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CalleeSavedRegs;
}
const TargetRegisterClass* const *BlackfinRegisterInfo::
getCalleeSavedRegClasses(const MachineFunction *MF) const {
using namespace BF;
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&PRegClass,
&DRegClass, &DRegClass, &DRegClass, &DRegClass,
&PRegClass, &PRegClass, &PRegClass,
0 };
return CalleeSavedRegClasses;
}
BitVector
BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
using namespace BF;

3
lib/Target/Blackfin/BlackfinRegisterInfo.h
View File

@ -33,9 +33,6 @@ namespace llvm {
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
// getSubReg implemented by tablegen

30
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -251,36 +251,6 @@ SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
return SPU_CalleeSaveRegs;
}
const TargetRegisterClass* const*
SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
{
// Cell ABI Calling Convention
static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
&SPU::GPRCRegClass, /* environment pointer */
&SPU::GPRCRegClass, /* stack pointer */
&SPU::GPRCRegClass, /* link register */
0 /* end */
};
return SPU_CalleeSaveRegClasses;
}
/*!
R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
generally unused) are the Cell's reserved registers

4
lib/Target/CellSPU/SPURegisterInfo.h
View File

@ -49,10 +49,6 @@ namespace llvm {
//! Return the array of callee-saved registers
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
//! Return the register class array of the callee-saved registers
virtual const TargetRegisterClass* const *
getCalleeSavedRegClasses(const MachineFunction *MF) const;
//! Allow for scavenging, so we can get scratch registers when needed.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
{ return true; }

16
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -148,22 +148,6 @@ getCalleeSavedRegs(const MachineFunction *MF) const {
return CalleeSavedRegs;
}
/// MBlaze Callee Saved Register Classes
const TargetRegisterClass* const* MBlazeRegisterInfo::
getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRC[] = {
&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
0
};
return CalleeSavedRC;
}
BitVector MBlazeRegisterInfo::
getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());

3
lib/Target/MBlaze/MBlazeRegisterInfo.h
View File

@ -54,9 +54,6 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction* MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;

42
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -71,48 +71,6 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
}
const TargetRegisterClass *const *
MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
const Function* F = MF->getFunction();
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
0
};
static const TargetRegisterClass * const CalleeSavedRegClassesFP[] = {
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, 0
};
static const TargetRegisterClass * const CalleeSavedRegClassesIntr[] = {
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
0
};
static const TargetRegisterClass * const CalleeSavedRegClassesIntrFP[] = {
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, &MSP430::GR16RegClass,
&MSP430::GR16RegClass, 0
};
if (hasFP(*MF))
return (F->getCallingConv() == CallingConv::MSP430_INTR ?
CalleeSavedRegClassesIntrFP : CalleeSavedRegClassesFP);
else
return (F->getCallingConv() == CallingConv::MSP430_INTR ?
CalleeSavedRegClassesIntr : CalleeSavedRegClasses);
}
BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());

3
lib/Target/MSP430/MSP430RegisterInfo.h
View File

@ -36,9 +36,6 @@ public:
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
const TargetRegisterClass* getPointerRegClass(unsigned Kind = 0) const;

28
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -116,34 +116,6 @@ getCalleeSavedRegs(const MachineFunction *MF) const
return BitMode32CalleeSavedRegs;
}
/// Mips Callee Saved Register Classes
const TargetRegisterClass* const*
MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
{
static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
&Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
};
static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
};
if (Subtarget.isSingleFloat())
return SingleFloatOnlyCalleeSavedRC;
else
return BitMode32CalleeSavedRC;
}
BitVector MipsRegisterInfo::
getReservedRegs(const MachineFunction &MF) const
{

3
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -42,9 +42,6 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction* MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;

7
lib/Target/PIC16/PIC16RegisterInfo.cpp
View File

@ -35,13 +35,6 @@ getCalleeSavedRegs(const MachineFunction *MF) const {
return CalleeSavedRegs;
}
// PIC16 Callee Saved Reg Classes
const TargetRegisterClass* const*
PIC16RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
return CalleeSavedRegClasses;
}
BitVector PIC16RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
return Reserved;

4
lib/Target/PIC16/PIC16RegisterInfo.h
View File

@ -41,10 +41,6 @@ class PIC16RegisterInfo : public PIC16GenRegisterInfo {
virtual const unsigned*
getCalleeSavedRegs(const MachineFunction *MF = 0) const;
// PIC16 callee saved register classes
virtual const TargetRegisterClass* const *
getCalleeSavedRegClasses(const MachineFunction *MF) const;
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
virtual bool hasFP(const MachineFunction &MF) const;

134
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -269,140 +269,6 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
// 32-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::GPRCRegClass, 0
};
// 32-bit SVR4 calling convention.
static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
&PPC::VRSAVERCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
0
};
// 64-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::G8RCRegClass, 0
};
// 64-bit SVR4 calling convention.
static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = {
&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
&PPC::VRSAVERCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
&PPC::CRBITRCRegClass,
0
};
if (Subtarget.isDarwinABI())
return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
Darwin32_CalleeSavedRegClasses;
return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses
: SVR4_CalleeSavedRegClasses;
}
// needsFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.

3
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -42,9 +42,6 @@ public:
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
/// targetHandlesStackFrameRounding - Returns true if the target is

7
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -52,13 +52,6 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
const TargetRegisterClass* const*
SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
return CalleeSavedRegClasses;
}
bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
return false;
}

3
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -32,9 +32,6 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const TargetRegisterClass* const* getCalleeSavedRegClasses(
const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;

16
lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -47,22 +47,6 @@ SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
SystemZRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
&SystemZ::FP64RegClass, &SystemZ::FP64RegClass, 0
};
return CalleeSavedRegClasses;
}
BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
if (hasFP(MF))

3
lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -32,9 +32,6 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const TargetRegisterClass* const* getCalleeSavedRegClasses(
const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
bool hasReservedCallFrame(MachineFunction &MF) const { return true; }

12
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -82,18 +82,6 @@ const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
0
};
return CalleeSavedRegClasses;
}
BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(XCore::CP);

3
lib/Target/XCore/XCoreRegisterInfo.h
View File

@ -44,9 +44,6 @@ public:
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const TargetRegisterClass* const* getCalleeSavedRegClasses(
const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;