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Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-06-09 16:03:19 +00:00
parent 622ab4ab50
commit 6f3661fdcd
9 changed files with 37 additions and 190 deletions
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16
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -56,9 +56,6 @@ namespace {
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O);
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O);
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
@ -307,19 +304,6 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
return false;
}
bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNum, unsigned AsmVariant,
const char *ExtraCode,
raw_ostream &O) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isReg() && "unexpected inline asm memory operand");
O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")";
return false;
}
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(opNum);

12
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -94,10 +94,6 @@ private:
inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps);
};
}
@ -466,14 +462,6 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
return ResNode;
}
bool MipsDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
OutOps.push_back(Op);
return false;
}
/// createMipsISelDag - This pass converts a legalized DAG into a
/// MIPS-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {

47
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -59,7 +59,6 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
default: return NULL;
}
}
@ -1190,9 +1189,6 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
SDValue MipsTargetLowering::
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
{
MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
unsigned StackAlignment =
getTargetMachine().getFrameLowering()->getStackAlignment();
assert(StackAlignment >=
@ -1215,14 +1211,24 @@ LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
// must be placed in the stack pointer register.
Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
SDValue());
// Retrieve updated $sp. There is a glue input to prevent instructions that
// clobber $sp from being inserted between copytoreg and copyfromreg.
SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32,
Chain.getValue(1));
// The stack space reserved by alloca is located right above the argument
// area. It is aligned on a boundary that is a multiple of StackAlignment.
MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) /
StackAlignment * StackAlignment;
SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
DAG.getConstant(SPOffset, MVT::i32));
// This node always has two return values: a new stack pointer
// value and a chain
SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other);
SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) };
return DAG.getMergeValues(Ops, 2, dl);
}
SDValue MipsTargetLowering::
@ -1764,10 +1770,6 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
if (IsPIC && !MipsFI->getGPFI())
MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
// Get the frame index of the stack frame object that points to the location
// of dynamically allocated area on the stack.
int DynAllocFI = MipsFI->getDynAllocFI();
// Update size of the maximum argument space.
// For O32, a minimum of four words (16 bytes) of argument space is
// allocated.
@ -1779,17 +1781,14 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
if (MaxCallFrameSize < NextStackOffset) {
MipsFI->setMaxCallFrameSize(NextStackOffset);
// Set the offsets relative to $sp of the $gp restore slot and dynamically
// allocated stack space. These offsets must be aligned to a boundary
// determined by the stack alignment of the ABI.
unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = (NextStackOffset + StackAlignment - 1) /
StackAlignment * StackAlignment;
if (IsPIC)
MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
MFI->setObjectOffset(DynAllocFI, NextStackOffset);
if (IsPIC) {
// $gp restore slot must be aligned.
unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = (NextStackOffset + StackAlignment - 1) /
StackAlignment * StackAlignment;
int GPFI = MipsFI->getGPFI();
MFI->setObjectOffset(GPFI, NextStackOffset);
}
}
// With EABI is it possible to have 16 args on registers.

4
lib/Target/Mips/MipsISelLowering.h
View File

@ -79,9 +79,7 @@ namespace llvm {
BuildPairF64,
ExtractElementF64,
WrapperPIC,
DynAlloc
WrapperPIC
};
}

16
lib/Target/Mips/MipsInstrInfo.td
View File

@ -39,9 +39,6 @@ def SDT_MipsDivRem : SDTypeProfile<0, 2,
def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
SDTCisVT<1, iPTR>]>;
// Call
def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
@ -102,10 +99,6 @@ def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
// Pointer to dynamically allocated stack area.
def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
[SDNPHasChain, SDNPInGlue]>;
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
@ -682,12 +675,6 @@ let addr=0 in
// can be matched. It's similar to Sparc LEA_ADDRi
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
// DynAlloc node points to dynamically allocated stack space.
// $sp is added to the list of implicitly used registers to prevent dead code
// elimination from removing instructions that modify $sp.
let Uses = [SP] in
def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
// MADD*/MSUB*
def MADD : MArithR<0, "madd", MipsMAdd, 1>;
def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
@ -865,9 +852,6 @@ def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
// select MipsDynAlloc
def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
//===----------------------------------------------------------------------===//
// Floating Point Support
//===----------------------------------------------------------------------===//

18
lib/Target/Mips/MipsMachineFunction.h
View File

@ -27,7 +27,6 @@ namespace llvm {
class MipsFunctionInfo : public MachineFunctionInfo {
private:
MachineFunction& MF;
/// SRetReturnReg - Some subtargets require that sret lowering includes
/// returning the value of the returned struct in a register. This field
/// holds the virtual register into which the sret argument is passed.
@ -48,7 +47,6 @@ private:
// LowerCall except for the frame object for restoring $gp.
std::pair<int, int> InArgFIRange, OutArgFIRange;
int GPFI; // Index of the frame object for restoring $gp
mutable int DynAllocFI; // Frame index of dynamically allocated stack area.
unsigned MaxCallFrameSize;
/// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap
@ -57,10 +55,10 @@ private:
int AtomicFrameIndex;
public:
MipsFunctionInfo(MachineFunction& MF)
: MF(MF), SRetReturnReg(0), GlobalBaseReg(0),
: SRetReturnReg(0), GlobalBaseReg(0),
VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0),
MaxCallFrameSize(0), AtomicFrameIndex(-1)
OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0),
AtomicFrameIndex(-1)
{}
bool isInArgFI(int FI) const {
@ -83,16 +81,6 @@ public:
bool needGPSaveRestore() const { return getGPFI(); }
bool isGPFI(int FI) const { return GPFI && GPFI == FI; }
// The first call to this function creates a frame object for dynamically
// allocated stack area.
int getDynAllocFI() const {
if (!DynAllocFI)
DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true);
return DynAllocFI;
}
bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; }
unsigned getSRetReturnReg() const { return SRetReturnReg; }
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }

10
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -177,14 +177,12 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
int Offset;
// Calculate final offset.
// - There is no need to change the offset if the frame object is one of the
// following: an outgoing argument, pointer to a dynamically allocated
// stack space or a $gp restore location,
// - There is no need to change the offset if the frame object is an outgoing
// argument or a $gp restore location,
// - If the frame object is any of the following, its offset must be adjusted
// by adding the size of the stack:
// incoming argument, callee-saved register location or local variable.
if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
MipsFI->isDynAllocFI(FrameIndex))
if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex))
Offset = spOffset;
else
Offset = spOffset + stackSize;
@ -213,7 +211,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
// 3. Locations for callee-saved registers.
// Everything else is referenced relative to whatever register
// getFrameRegister() returns.
if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
if (MipsFI->isOutArgFI(FrameIndex) ||
(FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
FrameReg = Mips::SP;
else

81
test/CodeGen/Mips/alloca.ll
View File

@ -4,15 +4,15 @@ define i32 @twoalloca(i32 %size) nounwind {
entry:
; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
; CHECK: addu $sp, $zero, $[[T0]]
; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]]
; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
; CHECK: addu $sp, $zero, $[[T2]]
; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp
; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]]
; CHECK: addu $sp, $zero, $[[T1]]
; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp
; CHECK: lw $25, %call16(foo)($gp)
; CHECK: addu $4, $zero, $[[T1]]
; CHECK: addiu $4, $[[SP1]], 24
; CHECK: jalr $25
; CHECK: lw $25, %call16(foo)($gp)
; CHECK: addu $4, $zero, $[[T3]]
; CHECK: addiu $4, $[[SP2]], 24
; CHECK: jalr $25
%tmp1 = alloca i8, i32 %size, align 4
%add.ptr = getelementptr inbounds i8* %tmp1, i32 5
@ -29,72 +29,3 @@ declare void @foo2(double, double, i32)
declare i32 @foo(i8*)
@.str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1
define i32 @alloca2(i32 %size) nounwind {
entry:
; dynamic allocated stack area and $gp restore slot have the same offsets
; relative to $sp.
;
; CHECK: alloca2
; CHECK: .cprestore [[OFF:[0-9]+]]
; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
; CHECK: addu $sp, $zero, $[[T0]]
; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]]
%tmp1 = alloca i8, i32 %size, align 4
%0 = bitcast i8* %tmp1 to i32*
%cmp = icmp sgt i32 %size, 10
br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry
; CHECK: addiu $4, $[[T1]], 40
%add.ptr = getelementptr inbounds i8* %tmp1, i32 40
%1 = bitcast i8* %add.ptr to i32*
call void @foo3(i32* %1) nounwind
%arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12
%.pre = bitcast i8* %arrayidx15.pre to i32*
br label %if.end
if.else: ; preds = %entry
; CHECK: addiu $4, $[[T1]], 12
%add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12
%2 = bitcast i8* %add.ptr5 to i32*
call void @foo3(i32* %2) nounwind
br label %if.end
if.end: ; preds = %if.else, %if.then
; CHECK: lw $5, 0($[[T1]])
; CHECK: lw $25, %call16(printf)
%.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ]
%tmp7 = load i32* %0, align 4, !tbaa !0
%arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4
%3 = bitcast i8* %arrayidx9 to i32*
%tmp10 = load i32* %3, align 4, !tbaa !0
%arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8
%4 = bitcast i8* %arrayidx12 to i32*
%tmp13 = load i32* %4, align 4, !tbaa !0
%tmp16 = load i32* %.pre-phi, align 4, !tbaa !0
%arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16
%5 = bitcast i8* %arrayidx18 to i32*
%tmp19 = load i32* %5, align 4, !tbaa !0
%arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20
%6 = bitcast i8* %arrayidx21 to i32*
%tmp22 = load i32* %6, align 4, !tbaa !0
%arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24
%7 = bitcast i8* %arrayidx24 to i32*
%tmp25 = load i32* %7, align 4, !tbaa !0
%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind
ret i32 0
}
declare void @foo3(i32*)
declare i32 @printf(i8* nocapture, ...) nounwind
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA", null}

23
test/CodeGen/Mips/inlineasmmemop.ll
View File

@ -1,23 +0,0 @@
; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
@g1 = external global i32
define i32 @f1(i32 %x) nounwind {
entry:
; CHECK: addiu $[[T0:[0-9]+]], $sp
; CHECK: #APP
; CHECK: sw $4, 0($[[T0]])
; CHECK: #NO_APP
; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
; CHECK: #APP
; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
; CHECK: #NO_APP
; CHECK: sw $[[T3]], 0($[[T1]])
%l1 = alloca i32, align 4
call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
%0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
store i32 %0, i32* @g1, align 4
ret i32 %0
}