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Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-03-22 14:14:49 +00:00
parent b7c2ed6664
commit 6fe310e155
4 changed files with 102 additions and 3 deletions
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82
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1536,6 +1536,7 @@ DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
unsigned W = fieldFromInstruction32(Insn, 21, 1);
unsigned P = fieldFromInstruction32(Insn, 24, 1);
unsigned Rt2 = Rt + 1;
bool writeback = (W == 1) | (P == 0);
@ -1547,7 +1548,86 @@ DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
if (Rt & 0x1) return MCDisassembler::Fail;
if (Rt & 0x1) S = MCDisassembler::SoftFail;
break;
default:
break;
}
switch (Inst.getOpcode()) {
case ARM::STRD:
case ARM::STRD_PRE:
case ARM::STRD_POST:
if (P == 0 && W == 1)
S = MCDisassembler::SoftFail;
if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
S = MCDisassembler::SoftFail;
if (type && Rm == 15)
S = MCDisassembler::SoftFail;
if (Rt2 == 15)
S = MCDisassembler::SoftFail;
if (!type && fieldFromInstruction32(Insn, 8, 4))
S = MCDisassembler::SoftFail;
break;
case ARM::STRH:
case ARM::STRH_PRE:
case ARM::STRH_POST:
if (Rt == 15)
S = MCDisassembler::SoftFail;
if (writeback && (Rn == 15 || Rn == Rt))
S = MCDisassembler::SoftFail;
if (!type && Rm == 15)
S = MCDisassembler::SoftFail;
break;
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
if (type && Rn == 15){
if (Rt2 == 15)
S = MCDisassembler::SoftFail;
break;
}
if (P == 0 && W == 1)
S = MCDisassembler::SoftFail;
if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
S = MCDisassembler::SoftFail;
if (!type && writeback && Rn == 15)
S = MCDisassembler::SoftFail;
if (writeback && (Rn == Rt || Rn == Rt2))
S = MCDisassembler::SoftFail;
break;
case ARM::LDRH:
case ARM::LDRH_PRE:
case ARM::LDRH_POST:
if (type && Rn == 15){
if (Rt == 15)
S = MCDisassembler::SoftFail;
break;
}
if (Rt == 15)
S = MCDisassembler::SoftFail;
if (!type && Rm == 15)
S = MCDisassembler::SoftFail;
if (!type && writeback && (Rn == 15 || Rn == Rt))
S = MCDisassembler::SoftFail;
break;
case ARM::LDRSH:
case ARM::LDRSH_PRE:
case ARM::LDRSH_POST:
case ARM::LDRSB:
case ARM::LDRSB_PRE:
case ARM::LDRSB_POST:
if (type && Rn == 15){
if (Rt == 15)
S = MCDisassembler::SoftFail;
break;
}
if (type && (Rt == 15 || (writeback && Rn == Rt)))
S = MCDisassembler::SoftFail;
if (!type && (Rt == 15 || Rm == 15))
S = MCDisassembler::SoftFail;
if (!type && writeback && (Rn == 15 || Rn == Rt))
S = MCDisassembler::SoftFail;
break;
default:
break;

2
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -201,7 +201,7 @@
0x20 0x51 0x17 0xe6
# CHECK: strdeq r2, r3, [r0], -r8
0xf8 0x24 0x00 0x00
0xf8 0x20 0x00 0x00
# CHECK: ldrdeq r2, r3, [r0], -r12
0xdc 0x24 0x00 0x00

16
test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt Normal file
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@ -0,0 +1,16 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: potentially undefined
# CHECK: 0xd1 0xf1 0x5f 0x01
0xd1 0xf1 0x5f 0x01
# CHECK: potentially undefined
# CHECK: 0xf1 0xf1 0x5f 0x01
0xf1 0xf1 0x5f 0x01
# CHECK: potentially undefined
# CHECK: 0xf1 0xf1 0x5f 0x01
0xf1 0xf1 0x5f 0x01
# CHECK: potentially undefined
# CHECK: 0xd1 0xe1 0x4f 0x01
0xd1 0xe1 0x4f 0x01

5
test/MC/Disassembler/ARM/invalid-LDRD-arm.txt → test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt
View File

@ -1,4 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
@ -7,4 +7,7 @@
#
# A8.6.68 LDRD (register)
# if Rt{0} = 1 then UNDEFINED;
# CHECK: potentially undefined
# CHECK: 0xd0 0x10 0x00 0x00
0xd0 0x10 0x00 0x00