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Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-03-22 13:24:43 +00:00
parent a0c48eb8f6
commit b7c2ed6664
3 changed files with 57 additions and 5 deletions
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6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -736,7 +736,7 @@ def postidx_reg : Operand<i32> {
let DecoderMethod = "DecodePostIdxReg";
let PrintMethod = "printPostIdxRegOperand";
let ParserMatchClass = PostIdxRegAsmOperand;
let MIOperandInfo = (ops GPR, i32imm);
let MIOperandInfo = (ops GPRnopc, i32imm);
}
@ -2484,7 +2484,7 @@ multiclass AI3ldrT<bits<4> op, string opc> {
let Inst{3-0} = offset{3-0};
let AsmMatchConverter = "cvtLdExtTWriteBackImm";
}
def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
(ins addr_offset_none:$addr, postidx_reg:$Rm),
IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
"\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
@ -2492,8 +2492,10 @@ multiclass AI3ldrT<bits<4> op, string opc> {
let Inst{23} = Rm{4};
let Inst{22} = 0;
let Inst{11-8} = 0;
let Unpredictable{11-8} = 0b1111;
let Inst{3-0} = Rm{3-0};
let AsmMatchConverter = "cvtLdExtTWriteBackReg";
let DecoderMethod = "DecodeLDR";
}
}

34
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -323,8 +323,8 @@ static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeLDR(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
#include "ARMGenEDInfo.inc"
@ -3178,7 +3178,7 @@ static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned add = fieldFromInstruction32(Insn, 4, 1);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(add));
@ -4263,3 +4263,31 @@ static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeLDR(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 16, 4);
unsigned Rt = fieldFromInstruction32(Val, 12, 4);
unsigned Rm = fieldFromInstruction32(Val, 0, 4);
Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
unsigned Cond = fieldFromInstruction32(Val, 28, 4);
if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}

22
test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt Normal file
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@ -0,0 +1,22 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: potentially undefined
# CHECK: 0xff 0x00 0xb9 0x00
0xff 0x00 0xb9 0x00
# CHECK: potentially undefined
# CHECK: 0xfb 0xf0 0xb9 0x00
0xfb 0xf0 0xb9 0x00
# CHECK: potentially undefined
# CHECK: 0xfb 0x01 0xb9 0x00
0xfb 0x01 0xb9 0x00
# CHECK: potentially undefined
# CHECK: 0xfb 0x00 0xbf 0x00
0xfb 0x00 0xbf 0x00
# CHECK: potentially undefined
# CHECK: 0xfb 0x90 0xb9 0x00
0xfb 0x90 0xb9 0x00