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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1536,6 +1536,7 @@ DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
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unsigned pred = fieldFromInstruction32(Insn, 28, 4);
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unsigned W = fieldFromInstruction32(Insn, 21, 1);
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unsigned P = fieldFromInstruction32(Insn, 24, 1);
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unsigned Rt2 = Rt + 1;
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bool writeback = (W == 1) | (P == 0);
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@ -1547,7 +1548,86 @@ DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
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case ARM::LDRD:
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case ARM::LDRD_PRE:
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case ARM::LDRD_POST:
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if (Rt & 0x1) return MCDisassembler::Fail;
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if (Rt & 0x1) S = MCDisassembler::SoftFail;
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break;
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default:
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break;
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}
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switch (Inst.getOpcode()) {
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case ARM::STRD:
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case ARM::STRD_PRE:
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case ARM::STRD_POST:
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if (P == 0 && W == 1)
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S = MCDisassembler::SoftFail;
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if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
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S = MCDisassembler::SoftFail;
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if (type && Rm == 15)
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S = MCDisassembler::SoftFail;
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if (Rt2 == 15)
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S = MCDisassembler::SoftFail;
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if (!type && fieldFromInstruction32(Insn, 8, 4))
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S = MCDisassembler::SoftFail;
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break;
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case ARM::STRH:
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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if (Rt == 15)
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S = MCDisassembler::SoftFail;
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if (writeback && (Rn == 15 || Rn == Rt))
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S = MCDisassembler::SoftFail;
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if (!type && Rm == 15)
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S = MCDisassembler::SoftFail;
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break;
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case ARM::LDRD:
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case ARM::LDRD_PRE:
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case ARM::LDRD_POST:
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if (type && Rn == 15){
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if (Rt2 == 15)
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S = MCDisassembler::SoftFail;
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break;
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}
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if (P == 0 && W == 1)
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S = MCDisassembler::SoftFail;
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if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
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S = MCDisassembler::SoftFail;
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if (!type && writeback && Rn == 15)
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S = MCDisassembler::SoftFail;
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if (writeback && (Rn == Rt || Rn == Rt2))
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S = MCDisassembler::SoftFail;
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break;
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case ARM::LDRH:
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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if (type && Rn == 15){
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if (Rt == 15)
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S = MCDisassembler::SoftFail;
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break;
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}
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if (Rt == 15)
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S = MCDisassembler::SoftFail;
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if (!type && Rm == 15)
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S = MCDisassembler::SoftFail;
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if (!type && writeback && (Rn == 15 || Rn == Rt))
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S = MCDisassembler::SoftFail;
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break;
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case ARM::LDRSH:
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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case ARM::LDRSB:
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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if (type && Rn == 15){
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if (Rt == 15)
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S = MCDisassembler::SoftFail;
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break;
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}
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if (type && (Rt == 15 || (writeback && Rn == Rt)))
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S = MCDisassembler::SoftFail;
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if (!type && (Rt == 15 || Rm == 15))
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S = MCDisassembler::SoftFail;
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if (!type && writeback && (Rn == 15 || Rn == Rt))
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S = MCDisassembler::SoftFail;
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break;
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default:
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break;
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@ -201,7 +201,7 @@
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0x20 0x51 0x17 0xe6
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# CHECK: strdeq r2, r3, [r0], -r8
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0xf8 0x24 0x00 0x00
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0xf8 0x20 0x00 0x00
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# CHECK: ldrdeq r2, r3, [r0], -r12
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0xdc 0x24 0x00 0x00
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16
test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt
Normal file
16
test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt
Normal file
@ -0,0 +1,16 @@
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# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
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# CHECK: potentially undefined
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# CHECK: 0xd1 0xf1 0x5f 0x01
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0xd1 0xf1 0x5f 0x01
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# CHECK: potentially undefined
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# CHECK: 0xf1 0xf1 0x5f 0x01
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0xf1 0xf1 0x5f 0x01
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# CHECK: potentially undefined
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# CHECK: 0xf1 0xf1 0x5f 0x01
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0xf1 0xf1 0x5f 0x01
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# CHECK: potentially undefined
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# CHECK: 0xd1 0xe1 0x4f 0x01
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0xd1 0xe1 0x4f 0x01
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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@ -7,4 +7,7 @@
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#
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# A8.6.68 LDRD (register)
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# if Rt{0} = 1 then UNDEFINED;
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# CHECK: potentially undefined
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# CHECK: 0xd0 0x10 0x00 0x00
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0xd0 0x10 0x00 0x00
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