6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-27 15:29:51 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies

Browse Source 
This prevents a future commit from regressing the load-i1.ll test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208887 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-05-15 14:41:55 +00:00
parent c1de569ce8
commit 704fe35d88
2 changed files with 28 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/R600/SIFixSGPRCopies.cpp
View File

@ -259,14 +259,17 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
break; break;
} }
case AMDGPU::INSERT_SUBREG: { case AMDGPU::INSERT_SUBREG: {
const TargetRegisterClass *DstRC, *SrcRC; const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
SrcRC = MRI.getRegClass(MI.getOperand(1).getReg()); Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
if (!TRI->isSGPRClass(DstRC) || !TRI->hasVGPRs(SrcRC)) Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
break; if (TRI->isSGPRClass(DstRC) &&
DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n"); (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
DEBUG(MI.print(dbgs())); DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
TII->moveToVALU(MI); DEBUG(MI.print(dbgs()));
TII->moveToVALU(MI);
}
break;
} }
} }
} }

18
lib/Target/R600/SIInstrInfo.cpp
View File

@ -691,6 +691,7 @@ bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
case AMDGPU::COPY: case AMDGPU::COPY:
case AMDGPU::REG_SEQUENCE: case AMDGPU::REG_SEQUENCE:
case AMDGPU::PHI: case AMDGPU::PHI:
case AMDGPU::INSERT_SUBREG:
return RI.hasVGPRs(getOpRegClass(MI, 0)); return RI.hasVGPRs(getOpRegClass(MI, 0));
default: default:
return RI.hasVGPRs(getOpRegClass(MI, OpNo)); return RI.hasVGPRs(getOpRegClass(MI, OpNo));
@ -924,6 +925,23 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
} }
} }
// Legalize INSERT_SUBREG
// src0 must have the same register class as dst
if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
unsigned Dst = MI->getOperand(0).getReg();
unsigned Src0 = MI->getOperand(1).getReg();
const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
if (DstRC != Src0RC) {
MachineBasicBlock &MBB = *MI->getParent();
unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
.addReg(Src0);
MI->getOperand(1).setReg(NewSrc0);
}
return;
}
// Legalize MUBUF* instructions // Legalize MUBUF* instructions
// FIXME: If we start using the non-addr64 instructions for compute, we // FIXME: If we start using the non-addr64 instructions for compute, we
// may need to legalize them here. // may need to legalize them here.