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R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
This prevents a future commit from regressing the load-i1.ll test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208887 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -259,14 +259,17 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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break;
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break;
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}
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}
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case AMDGPU::INSERT_SUBREG: {
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case AMDGPU::INSERT_SUBREG: {
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const TargetRegisterClass *DstRC, *SrcRC;
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const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
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DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
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DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
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SrcRC = MRI.getRegClass(MI.getOperand(1).getReg());
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Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
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if (!TRI->isSGPRClass(DstRC) || !TRI->hasVGPRs(SrcRC))
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Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
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break;
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if (TRI->isSGPRClass(DstRC) &&
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DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
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(TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
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DEBUG(MI.print(dbgs()));
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DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
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TII->moveToVALU(MI);
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DEBUG(MI.print(dbgs()));
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TII->moveToVALU(MI);
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}
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break;
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}
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}
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}
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}
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}
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}
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@ -691,6 +691,7 @@ bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
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case AMDGPU::COPY:
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case AMDGPU::COPY:
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case AMDGPU::REG_SEQUENCE:
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case AMDGPU::REG_SEQUENCE:
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case AMDGPU::PHI:
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case AMDGPU::PHI:
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case AMDGPU::INSERT_SUBREG:
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return RI.hasVGPRs(getOpRegClass(MI, 0));
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return RI.hasVGPRs(getOpRegClass(MI, 0));
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default:
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default:
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return RI.hasVGPRs(getOpRegClass(MI, OpNo));
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return RI.hasVGPRs(getOpRegClass(MI, OpNo));
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@ -924,6 +925,23 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
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}
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}
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}
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}
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// Legalize INSERT_SUBREG
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// src0 must have the same register class as dst
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if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
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unsigned Dst = MI->getOperand(0).getReg();
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unsigned Src0 = MI->getOperand(1).getReg();
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
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const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
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if (DstRC != Src0RC) {
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MachineBasicBlock &MBB = *MI->getParent();
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unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
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.addReg(Src0);
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MI->getOperand(1).setReg(NewSrc0);
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}
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return;
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}
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// Legalize MUBUF* instructions
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// Legalize MUBUF* instructions
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// FIXME: If we start using the non-addr64 instructions for compute, we
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// FIXME: If we start using the non-addr64 instructions for compute, we
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// may need to legalize them here.
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// may need to legalize them here.
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