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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-19 19:31:50 +00:00
Remove redundant instructions.
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
81b441151f
commit
70564a9c19
@ -818,7 +818,6 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
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@ -858,8 +857,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// ori tmp3,$0,255 # 0xff
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// sll mask,tmp3,shift
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// nor mask2,$0,mask
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// andi tmp4,incr,255
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// sll incr2,tmp4,shift
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// sll incr2,incr,shift
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int64_t MaskImm = (Size == 1) ? 255 : 65535;
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BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
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@ -869,8 +867,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
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BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
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BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
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BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
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BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
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BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(Shift);
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// atomic.load.binop
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@ -886,8 +883,9 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// atomic.swap
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// loopMBB:
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// ll oldval,0(addr)
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// and newval,incr2,mask
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// and tmp8,oldval,mask2
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// or tmp9,tmp8,incr2
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// or tmp9,tmp8,newval
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// sc tmp9,0(addr)
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// beq tmp9,$0,loopMBB
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@ -898,17 +896,17 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// nor tmp7, $0, tmp6
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2);
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BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
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BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
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} else if (BinOpcode) {
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// <binop> tmp7, oldval, incr2
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BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2);
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}
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if (BinOpcode != 0 || Nand)
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BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
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} else {// atomic.swap
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BuildMI(BB, dl, TII->get(Mips::ANDi), Newval).addReg(Incr2).addReg(Mask);
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}
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2);
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if (BinOpcode != 0 || Nand)
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BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval);
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else
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BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Incr2);
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BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval);
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp13)
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.addReg(Tmp9).addReg(Addr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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@ -953,7 +951,6 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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unsigned Oldval = MI->getOperand(2).getReg();
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unsigned Newval = MI->getOperand(3).getReg();
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unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
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// insert new blocks after the current block
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@ -991,12 +988,10 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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.addReg(Dest).addReg(Oldval).addMBB(exitMBB);
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// loop2MBB:
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// or tmp1, $0, newval
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// sc tmp1, 0(ptr)
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// beq tmp1, $0, loop1MBB
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BB = loop2MBB;
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BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Newval);
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Newval).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB);
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@ -1068,6 +1063,7 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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loop2MBB->addSuccessor(sinkMBB);
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sinkMBB->addSuccessor(exitMBB);
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// FIXME: computation of newval2 can be moved to loop2MBB.
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// thisMBB:
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// addiu tmp1,$0,-4 # 0xfffffffc
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// and addr,ptr,tmp1
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@ -73,8 +73,7 @@ entry:
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $2, 0($[[R0]])
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; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
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; CHECK: or $[[R2:[0-9]+]], $zero, $5
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; CHECK: sc $[[R2]], 0($[[R0]])
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; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK: beq $[[R2]], $zero, $[[BB0]]
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; CHECK: $[[BB1]]:
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}
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@ -97,8 +96,7 @@ entry:
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: andi $[[R8:[0-9]+]], $4, 255
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; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
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; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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@ -129,8 +127,7 @@ entry:
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: andi $[[R8:[0-9]+]], $4, 255
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; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
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; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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@ -161,8 +158,7 @@ entry:
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: andi $[[R8:[0-9]+]], $4, 255
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; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
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; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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@ -194,8 +190,7 @@ entry:
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: andi $[[R8:[0-9]+]], $4, 255
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; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
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; CHECK: sll $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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