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https://github.com/c64scene-ar/llvm-6502.git
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implement div and rem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24798 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -65,6 +65,10 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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computeRegisterProperties();
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}
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@ -278,8 +282,30 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::SDIV:
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case ISD::UDIV: {
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDOperand DivLHS = Select(N->getOperand(0));
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SDOperand DivRHS = Select(N->getOperand(1));
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// Set the Y register to the high-part.
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SDOperand TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32));
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} else {
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TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
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}
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TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
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CurDAG->getRegister(V8::G0, MVT::i32));
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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// FIXME: Handle mul by immediate.
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SDOperand MulLHS = Select(N->getOperand(0));
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SDOperand MulRHS = Select(N->getOperand(1));
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
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@ -65,6 +65,10 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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computeRegisterProperties();
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}
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@ -278,8 +282,30 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::SDIV:
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case ISD::UDIV: {
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDOperand DivLHS = Select(N->getOperand(0));
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SDOperand DivRHS = Select(N->getOperand(1));
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// Set the Y register to the high-part.
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SDOperand TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32));
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} else {
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TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
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}
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TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
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CurDAG->getRegister(V8::G0, MVT::i32));
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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// FIXME: Handle mul by immediate.
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SDOperand MulLHS = Select(N->getOperand(0));
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SDOperand MulRHS = Select(N->getOperand(1));
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
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