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Add isConditionalMove bits to X86 and ARM instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-09-23 22:57:01 +00:00
parent 5716180b1a
commit 71e416ac3a
5 changed files with 10 additions and 10 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
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@ -2391,7 +2391,7 @@ def BCCZi64 : PseudoInst<(outs),
// Conditional moves // Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1, isConditionalMove = 1 in {
def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
IIC_iCMOVr, "mov", "\t$dst, $true", IIC_iCMOVr, "mov", "\t$dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
@ -2415,7 +2415,7 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
RegConstraint<"$false = $dst">, UnaryDP { RegConstraint<"$false = $dst">, UnaryDP {
let Inst{25} = 1; let Inst{25} = 1;
} }
} // neverHasSideEffects } // neverHasSideEffects, isConditionalMove
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Atomic operations intrinsics // Atomic operations intrinsics

4
lib/Target/ARM/ARMInstrThumb.td
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@ -866,7 +866,7 @@ let usesCustomInserter = 1 in // Expanded after instruction selection.
// 16-bit movcc in IT blocks for Thumb2. // 16-bit movcc in IT blocks for Thumb2.
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1, isConditionalMove = 1 in {
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr, def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
"mov", "\t$dst, $rhs", []>, "mov", "\t$dst, $rhs", []>,
T1Special<{1,0,?,?}>; T1Special<{1,0,?,?}>;
@ -874,7 +874,7 @@ def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi, def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
"mov", "\t$dst, $rhs", []>, "mov", "\t$dst, $rhs", []>,
T1General<{1,0,0,?,?}>; T1General<{1,0,0,?,?}>;
} // neverHasSideEffects } // neverHasSideEffects, isConditionalMove
// tLEApcrel - Load a pc-relative address into a register without offending the // tLEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.

4
lib/Target/ARM/ARMInstrThumb2.td
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@ -2169,7 +2169,7 @@ defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
// Conditional moves // Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1, isConditionalMove = 1 in {
def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr, def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
"mov", ".w\t$dst, $true", "mov", ".w\t$dst, $true",
[/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
@ -2221,7 +2221,7 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
(ins rGPR:$false, rGPR:$true, i32imm:$rhs), (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>, IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
} // neverHasSideEffects } // neverHasSideEffects, isConditionalMove
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Atomic operations intrinsics // Atomic operations intrinsics

4
lib/Target/X86/X86Instr64bit.td
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@ -1366,7 +1366,7 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
} // Defs = [EFLAGS] } // Defs = [EFLAGS]
// Conditional moves // Conditional moves
let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { let isConditionalMove = 1, Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
let isCommutable = 1 in { let isCommutable = 1 in {
def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@ -1530,7 +1530,7 @@ def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
"cmovno{q}\t{$src2, $dst|$dst, $src2}", "cmovno{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
X86_COND_NO, EFLAGS))]>, TB; X86_COND_NO, EFLAGS))]>, TB;
} // Constraints = "$src1 = $dst" } // isConditionalMove, Constraints = "$src1 = $dst"
// Use sbb to materialize carry flag into a GPR. // Use sbb to materialize carry flag into a GPR.
// FIXME: This are pseudo ops that should be replaced with Pat<> patterns. // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.

4
lib/Target/X86/X86InstrInfo.td
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@ -1269,7 +1269,7 @@ let Constraints = "$src1 = $dst" in {
// Conditional moves // Conditional moves
let Uses = [EFLAGS] in { let Uses = [EFLAGS] in {
let Predicates = [HasCMov] in { let isConditionalMove = 1, Predicates = [HasCMov] in {
let isCommutable = 1 in { let isCommutable = 1 in {
def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
@ -1657,7 +1657,7 @@ def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
X86_COND_NO, EFLAGS))]>, X86_COND_NO, EFLAGS))]>,
TB; TB;
} // Predicates = [HasCMov] } // isConditionalMove, Predicates = [HasCMov]
// X86 doesn't have 8-bit conditional moves. Use a customInserter to // X86 doesn't have 8-bit conditional moves. Use a customInserter to
// emit control flow. An alternative to this is to mark i8 SELECT as Promote, // emit control flow. An alternative to this is to mark i8 SELECT as Promote,