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[CodeGen] Add print and verify pass after each MachineFunctionPass by default

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Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.

To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2014-12-11 19:42:05 +00:00
parent 9173c775e3
commit 71f56c4aac
14 changed files with 205 additions and 262 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
include/llvm/CodeGen/Passes.h
View File

@ -105,6 +105,7 @@ private:
AnalysisID StopAfter; AnalysisID StopAfter;
bool Started; bool Started;
bool Stopped; bool Stopped;
bool AddingMachinePasses;
protected: protected:
TargetMachine *TM; TargetMachine *TM;
@ -259,12 +260,9 @@ protected:
return false; return false;
} }
/// addPreRegAlloc - This method may be implemented by targets that want to /// This method may be implemented by targets that want to run passes
/// run passes immediately before register allocation. This should return /// immediately before register allocation.
/// true if -print-machineinstrs should print after these passes. virtual void addPreRegAlloc() { }
virtual bool addPreRegAlloc() {
return false;
}
/// createTargetRegisterAllocator - Create the register allocator pass for /// createTargetRegisterAllocator - Create the register allocator pass for
/// this target at the current optimization level. /// this target at the current optimization level.
@ -290,24 +288,16 @@ protected:
return false; return false;
} }
/// addPostRegAlloc - This method may be implemented by targets that want to /// This method may be implemented by targets that want to run passes after
/// run passes after register allocation pass pipeline but before /// register allocation pass pipeline but before prolog-epilog insertion.
/// prolog-epilog insertion. This should return true if -print-machineinstrs virtual void addPostRegAlloc() { }
/// should print after these passes.
virtual bool addPostRegAlloc() {
return false;
}
/// Add passes that optimize machine instructions after register allocation. /// Add passes that optimize machine instructions after register allocation.
virtual void addMachineLateOptimization(); virtual void addMachineLateOptimization();
/// addPreSched2 - This method may be implemented by targets that want to /// This method may be implemented by targets that want to run passes after
/// run passes after prolog-epilog insertion and before the second instruction /// prolog-epilog insertion and before the second instruction scheduling pass.
/// scheduling pass. This should return true if -print-machineinstrs should virtual void addPreSched2() { }
/// print after these passes.
virtual bool addPreSched2() {
return false;
}
/// addGCPasses - Add late codegen passes that analyze code for garbage /// addGCPasses - Add late codegen passes that analyze code for garbage
/// collection. This should return true if GC info should be printed after /// collection. This should return true if GC info should be printed after
@ -317,24 +307,30 @@ protected:
/// Add standard basic block placement passes. /// Add standard basic block placement passes.
virtual void addBlockPlacement(); virtual void addBlockPlacement();
/// addPreEmitPass - This pass may be implemented by targets that want to run /// This pass may be implemented by targets that want to run passes
/// passes immediately before machine code is emitted. This should return /// immediately before machine code is emitted.
/// true if -print-machineinstrs should print out the code after the passes. virtual void addPreEmitPass() { }
virtual bool addPreEmitPass() {
return false;
}
/// Utilities for targets to add passes to the pass manager. /// Utilities for targets to add passes to the pass manager.
/// ///
/// Add a CodeGen pass at this point in the pipeline after checking overrides. /// Add a CodeGen pass at this point in the pipeline after checking overrides.
/// Return the pass that was added, or zero if no pass was added. /// Return the pass that was added, or zero if no pass was added.
AnalysisID addPass(AnalysisID PassID); /// @p printAfter if true and adding a machine function pass add an extra
/// machine printer pass afterwards
/// @p verifyAfter if true and adding a machine function pass add an extra
/// machine verification pass afterwards.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
bool printAfter = true);
/// Add a pass to the PassManager if that pass is supposed to be run, as /// Add a pass to the PassManager if that pass is supposed to be run, as
/// determined by the StartAfter and StopAfter options. Takes ownership of the /// determined by the StartAfter and StopAfter options. Takes ownership of the
/// pass. /// pass.
void addPass(Pass *P); /// @p printAfter if true and adding a machine function pass add an extra
/// machine printer pass afterwards
/// @p verifyAfter if true and adding a machine function pass add an extra
/// machine verification pass afterwards.
void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
/// addMachinePasses helper to create the target-selected or overriden /// addMachinePasses helper to create the target-selected or overriden
/// regalloc pass. /// regalloc pass.
@ -343,7 +339,14 @@ protected:
/// printAndVerify - Add a pass to dump then verify the machine function, if /// printAndVerify - Add a pass to dump then verify the machine function, if
/// those steps are enabled. /// those steps are enabled.
/// ///
void printAndVerify(const char *Banner); void printAndVerify(const std::string &Banner);
/// Add a pass to print the machine function if printing is enabled.
void addPrintPass(const std::string &Banner);
/// Add a pass to perform basic verification of the machine function if
/// verification is enabled.
void addVerifyPass(const std::string &Banner);
}; };
} // namespace llvm } // namespace llvm

133
lib/CodeGen/Passes.cpp
View File

@ -235,8 +235,8 @@ TargetPassConfig::~TargetPassConfig() {
// registers all common codegen passes. // registers all common codegen passes.
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr), : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
Started(true), Stopped(false), TM(tm), Impl(nullptr), Initialized(false), Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
DisableVerify(false), Impl(nullptr), Initialized(false), DisableVerify(false),
EnableTailMerge(true) { EnableTailMerge(true) {
Impl = new PassConfigImpl(); Impl = new PassConfigImpl();
@ -304,7 +304,7 @@ IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
/// a later pass or that it should stop after an earlier pass, then do not add /// a later pass or that it should stop after an earlier pass, then do not add
/// the pass. Finally, compare the current pass against the StartAfter /// the pass. Finally, compare the current pass against the StartAfter
/// and StopAfter options and change the Started/Stopped flags accordingly. /// and StopAfter options and change the Started/Stopped flags accordingly.
void TargetPassConfig::addPass(Pass *P) { void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
assert(!Initialized && "PassConfig is immutable"); assert(!Initialized && "PassConfig is immutable");
// Cache the Pass ID here in case the pass manager finds this pass is // Cache the Pass ID here in case the pass manager finds this pass is
@ -313,10 +313,18 @@ void TargetPassConfig::addPass(Pass *P) {
// and shouldn't reference it. // and shouldn't reference it.
AnalysisID PassID = P->getPassID(); AnalysisID PassID = P->getPassID();
if (Started && !Stopped) if (Started && !Stopped) {
PM->add(P); PM->add(P);
else if (AddingMachinePasses) {
std::string Banner = std::string("After ")+std::string(P->getPassName());
if (printAfter)
addPrintPass(Banner);
if (verifyAfter)
addVerifyPass(Banner);
}
} else {
delete P; delete P;
}
if (StopAfter == PassID) if (StopAfter == PassID)
Stopped = true; Stopped = true;
if (StartAfter == PassID) if (StartAfter == PassID)
@ -330,7 +338,8 @@ void TargetPassConfig::addPass(Pass *P) {
/// ///
/// addPass cannot return a pointer to the pass instance because is internal the /// addPass cannot return a pointer to the pass instance because is internal the
/// PassManager and the instance we create here may already be freed. /// PassManager and the instance we create here may already be freed.
AnalysisID TargetPassConfig::addPass(AnalysisID PassID) { AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
bool printAfter) {
IdentifyingPassPtr TargetID = getPassSubstitution(PassID); IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
if (!FinalPtr.isValid()) if (!FinalPtr.isValid())
@ -345,7 +354,7 @@ AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
llvm_unreachable("Pass ID not registered"); llvm_unreachable("Pass ID not registered");
} }
AnalysisID FinalID = P->getPassID(); AnalysisID FinalID = P->getPassID();
addPass(P); // Ends the lifetime of P. addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
// Add the passes after the pass P if there is any. // Add the passes after the pass P if there is any.
for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
@ -360,18 +369,25 @@ AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
NP = Pass::createPass((*I).second.getID()); NP = Pass::createPass((*I).second.getID());
assert(NP && "Pass ID not registered"); assert(NP && "Pass ID not registered");
} }
addPass(NP); addPass(NP, false, false);
} }
} }
return FinalID; return FinalID;
} }
void TargetPassConfig::printAndVerify(const char *Banner) { void TargetPassConfig::printAndVerify(const std::string &Banner) {
if (TM->shouldPrintMachineCode()) addPrintPass(Banner);
addPass(createMachineFunctionPrinterPass(dbgs(), Banner)); addVerifyPass(Banner);
}
void TargetPassConfig::addPrintPass(const std::string &Banner) {
if (TM->shouldPrintMachineCode())
PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
}
void TargetPassConfig::addVerifyPass(const std::string &Banner) {
if (VerifyMachineCode) if (VerifyMachineCode)
addPass(createMachineVerifierPass(Banner)); PM->add(createMachineVerifierPass(Banner));
} }
/// Add common target configurable passes that perform LLVM IR to IR transforms /// Add common target configurable passes that perform LLVM IR to IR transforms
@ -491,6 +507,8 @@ void TargetPassConfig::addISelPrepare() {
/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
/// before/after any target-independent pass. But it's currently overkill. /// before/after any target-independent pass. But it's currently overkill.
void TargetPassConfig::addMachinePasses() { void TargetPassConfig::addMachinePasses() {
AddingMachinePasses = true;
// Insert a machine instr printer pass after the specified pass. // Insert a machine instr printer pass after the specified pass.
// If -print-machineinstrs specified, print machineinstrs after all passes. // If -print-machineinstrs specified, print machineinstrs after all passes.
if (StringRef(PrintMachineInstrs.getValue()).equals("")) if (StringRef(PrintMachineInstrs.getValue()).equals(""))
@ -510,8 +528,7 @@ void TargetPassConfig::addMachinePasses() {
printAndVerify("After Instruction Selection"); printAndVerify("After Instruction Selection");
// Expand pseudo-instructions emitted by ISel. // Expand pseudo-instructions emitted by ISel.
if (addPass(&ExpandISelPseudosID)) addPass(&ExpandISelPseudosID);
printAndVerify("After ExpandISelPseudos");
// Add passes that optimize machine instructions in SSA form. // Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
@ -519,12 +536,11 @@ void TargetPassConfig::addMachinePasses() {
} else { } else {
// If the target requests it, assign local variables to stack slots relative // If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible. // to one another and simplify frame index references where possible.
addPass(&LocalStackSlotAllocationID); addPass(&LocalStackSlotAllocationID, false);
} }
// Run pre-ra passes. // Run pre-ra passes.
if (addPreRegAlloc()) addPreRegAlloc();
printAndVerify("After PreRegAlloc passes");
// Run register allocation and passes that are tightly coupled with it, // Run register allocation and passes that are tightly coupled with it,
// including phi elimination and scheduling. // including phi elimination and scheduling.
@ -534,12 +550,10 @@ void TargetPassConfig::addMachinePasses() {
addFastRegAlloc(createRegAllocPass(false)); addFastRegAlloc(createRegAllocPass(false));
// Run post-ra passes. // Run post-ra passes.
if (addPostRegAlloc()) addPostRegAlloc();
printAndVerify("After PostRegAlloc passes");
// Insert prolog/epilog code. Eliminate abstract frame index references... // Insert prolog/epilog code. Eliminate abstract frame index references...
addPass(&PrologEpilogCodeInserterID); addPass(&PrologEpilogCodeInserterID);
printAndVerify("After PrologEpilogCodeInserter");
/// Add passes that optimize machine instructions after register allocation. /// Add passes that optimize machine instructions after register allocation.
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
@ -547,11 +561,9 @@ void TargetPassConfig::addMachinePasses() {
// Expand pseudo instructions before second scheduling pass. // Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID); addPass(&ExpandPostRAPseudosID);
printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes. // Run pre-sched2 passes.
if (addPreSched2()) addPreSched2();
printAndVerify("After PreSched2 passes");
// Second pass scheduler. // Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
@ -559,66 +571,61 @@ void TargetPassConfig::addMachinePasses() {
addPass(&PostMachineSchedulerID); addPass(&PostMachineSchedulerID);
else else
addPass(&PostRASchedulerID); addPass(&PostRASchedulerID);
printAndVerify("After PostRAScheduler");
} }
// GC // GC
if (addGCPasses()) { if (addGCPasses()) {
if (PrintGCInfo) if (PrintGCInfo)
addPass(createGCInfoPrinter(dbgs())); addPass(createGCInfoPrinter(dbgs()), false, false);
} }
// Basic block placement. // Basic block placement.
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addBlockPlacement(); addBlockPlacement();
if (addPreEmitPass()) addPreEmitPass();
printAndVerify("After PreEmit passes");
addPass(&StackMapLivenessID); addPass(&StackMapLivenessID, false);
AddingMachinePasses = false;
} }
/// Add passes that optimize machine instructions in SSA form. /// Add passes that optimize machine instructions in SSA form.
void TargetPassConfig::addMachineSSAOptimization() { void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication. // Pre-ra tail duplication.
if (addPass(&EarlyTailDuplicateID)) addPass(&EarlyTailDuplicateID);
printAndVerify("After Pre-RegAlloc TailDuplicate");
// Optimize PHIs before DCE: removing dead PHI cycles may make more // Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead. // instructions dead.
addPass(&OptimizePHIsID); addPass(&OptimizePHIsID, false);
// This pass merges large allocas. StackSlotColoring is a different pass // This pass merges large allocas. StackSlotColoring is a different pass
// which merges spill slots. // which merges spill slots.
addPass(&StackColoringID); addPass(&StackColoringID, false);
// If the target requests it, assign local variables to stack slots relative // If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible. // to one another and simplify frame index references where possible.
addPass(&LocalStackSlotAllocationID); addPass(&LocalStackSlotAllocationID, false);
// With optimization, dead code should already be eliminated. However // With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only // there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack // used by tail calls, where the tail calls reuse the incoming stack
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
addPass(&DeadMachineInstructionElimID); addPass(&DeadMachineInstructionElimID);
printAndVerify("After codegen DCE pass");
// Allow targets to insert passes that improve instruction level parallelism, // Allow targets to insert passes that improve instruction level parallelism,
// like if-conversion. Such passes will typically need dominator trees and // like if-conversion. Such passes will typically need dominator trees and
// loop info, just like LICM and CSE below. // loop info, just like LICM and CSE below.
if (addILPOpts()) addILPOpts();
printAndVerify("After ILP optimizations");
addPass(&MachineLICMID); addPass(&MachineLICMID, false);
addPass(&MachineCSEID); addPass(&MachineCSEID, false);
addPass(&MachineSinkingID); addPass(&MachineSinkingID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
addPass(&PeepholeOptimizerID); addPass(&PeepholeOptimizerID, false);
// Clean-up the dead code that may have been generated by peephole // Clean-up the dead code that may have been generated by peephole
// rewriting. // rewriting.
addPass(&DeadMachineInstructionElimID); addPass(&DeadMachineInstructionElimID);
printAndVerify("After codegen peephole optimization pass");
} }
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
@ -701,18 +708,17 @@ bool TargetPassConfig::usingDefaultRegAlloc() const {
/// Add the minimum set of target-independent passes that are required for /// Add the minimum set of target-independent passes that are required for
/// register allocation. No coalescing or scheduling. /// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(&PHIEliminationID); addPass(&PHIEliminationID, false);
addPass(&TwoAddressInstructionPassID); addPass(&TwoAddressInstructionPassID, false);
addPass(RegAllocPass); addPass(RegAllocPass);
printAndVerify("After Register Allocation");
} }
/// Add standard target-independent passes that are tightly coupled with /// Add standard target-independent passes that are tightly coupled with
/// optimized register allocation, including coalescing, machine instruction /// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself. /// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
addPass(&ProcessImplicitDefsID); addPass(&ProcessImplicitDefsID, false);
// LiveVariables currently requires pure SSA form. // LiveVariables currently requires pure SSA form.
// //
@ -720,35 +726,30 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
// LiveVariables can be removed completely, and LiveIntervals can be directly // LiveVariables can be removed completely, and LiveIntervals can be directly
// computed. (We still either need to regenerate kill flags after regalloc, or // computed. (We still either need to regenerate kill flags after regalloc, or
// preferably fix the scavenger to not depend on them). // preferably fix the scavenger to not depend on them).
addPass(&LiveVariablesID); addPass(&LiveVariablesID, false);
// Edge splitting is smarter with machine loop info. // Edge splitting is smarter with machine loop info.
addPass(&MachineLoopInfoID); addPass(&MachineLoopInfoID, false);
addPass(&PHIEliminationID); addPass(&PHIEliminationID, false);
// Eventually, we want to run LiveIntervals before PHI elimination. // Eventually, we want to run LiveIntervals before PHI elimination.
if (EarlyLiveIntervals) if (EarlyLiveIntervals)
addPass(&LiveIntervalsID); addPass(&LiveIntervalsID, false);
addPass(&TwoAddressInstructionPassID); addPass(&TwoAddressInstructionPassID, false);
addPass(&RegisterCoalescerID); addPass(&RegisterCoalescerID);
printAndVerify("After Register Coalescing");
// PreRA instruction scheduling. // PreRA instruction scheduling.
if (addPass(&MachineSchedulerID)) addPass(&MachineSchedulerID);
printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass. // Add the selected register allocation pass.
addPass(RegAllocPass); addPass(RegAllocPass);
printAndVerify("After Register Allocation, before rewriter");
// Allow targets to change the register assignments before rewriting. // Allow targets to change the register assignments before rewriting.
if (addPreRewrite()) addPreRewrite();
printAndVerify("After pre-rewrite passes");
// Finally rewrite virtual registers. // Finally rewrite virtual registers.
addPass(&VirtRegRewriterID); addPass(&VirtRegRewriterID);
printAndVerify("After Virtual Register Rewriter");
// Perform stack slot coloring and post-ra machine LICM. // Perform stack slot coloring and post-ra machine LICM.
// //
@ -760,8 +761,6 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
// //
// FIXME: can this move into MachineLateOptimization? // FIXME: can this move into MachineLateOptimization?
addPass(&PostRAMachineLICMID); addPass(&PostRAMachineLICMID);
printAndVerify("After StackSlotColoring and postra Machine LICM");
} }
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
@ -771,34 +770,30 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
/// Add passes that optimize machine instructions after register allocation. /// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOptimization() { void TargetPassConfig::addMachineLateOptimization() {
// Branch folding must be run after regalloc and prolog/epilog insertion. // Branch folding must be run after regalloc and prolog/epilog insertion.
if (addPass(&BranchFolderPassID)) addPass(&BranchFolderPassID);
printAndVerify("After BranchFolding");
// Tail duplication. // Tail duplication.
// Note that duplicating tail just increases code size and degrades // Note that duplicating tail just increases code size and degrades
// performance for targets that require Structured Control Flow. // performance for targets that require Structured Control Flow.
// In addition it can also make CFG irreducible. Thus we disable it. // In addition it can also make CFG irreducible. Thus we disable it.
if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID)) if (!TM->requiresStructuredCFG())
printAndVerify("After TailDuplicate"); addPass(&TailDuplicateID);
// Copy propagation. // Copy propagation.
if (addPass(&MachineCopyPropagationID)) addPass(&MachineCopyPropagationID);
printAndVerify("After copy propagation pass");
} }
/// Add standard GC passes. /// Add standard GC passes.
bool TargetPassConfig::addGCPasses() { bool TargetPassConfig::addGCPasses() {
addPass(&GCMachineCodeAnalysisID); addPass(&GCMachineCodeAnalysisID, false);
return true; return true;
} }
/// Add standard basic block placement passes. /// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() { void TargetPassConfig::addBlockPlacement() {
if (addPass(&MachineBlockPlacementID)) { if (addPass(&MachineBlockPlacementID, false)) {
// Run a separate pass to collect block placement statistics. // Run a separate pass to collect block placement statistics.
if (EnableBlockPlacementStats) if (EnableBlockPlacementStats)
addPass(&MachineBlockPlacementStatsID); addPass(&MachineBlockPlacementStatsID);
printAndVerify("After machine block placement.");
} }
} }

30
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -181,10 +181,10 @@ public:
bool addPreISel() override; bool addPreISel() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addILPOpts() override; bool addILPOpts() override;
bool addPreRegAlloc() override; void addPreRegAlloc() override;
bool addPostRegAlloc() override; void addPostRegAlloc() override;
bool addPreSched2() override; void addPreSched2() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -267,47 +267,43 @@ bool AArch64PassConfig::addILPOpts() {
return true; return true;
} }
bool AArch64PassConfig::addPreRegAlloc() { void AArch64PassConfig::addPreRegAlloc() {
// Use AdvSIMD scalar instructions whenever profitable. // Use AdvSIMD scalar instructions whenever profitable.
if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) { if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
addPass(createAArch64AdvSIMDScalar()); addPass(createAArch64AdvSIMDScalar(), false);
// The AdvSIMD pass may produce copies that can be rewritten to // The AdvSIMD pass may produce copies that can be rewritten to
// be register coaleascer friendly. // be register coaleascer friendly.
addPass(&PeepholeOptimizerID); addPass(&PeepholeOptimizerID);
} }
return true;
} }
bool AArch64PassConfig::addPostRegAlloc() { void AArch64PassConfig::addPostRegAlloc() {
// Change dead register definitions to refer to the zero register. // Change dead register definitions to refer to the zero register.
if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination) if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions()); addPass(createAArch64DeadRegisterDefinitions(), false);
if (TM->getOptLevel() != CodeGenOpt::None && if (TM->getOptLevel() != CodeGenOpt::None &&
(TM->getSubtarget<AArch64Subtarget>().isCortexA53() || (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
TM->getSubtarget<AArch64Subtarget>().isCortexA57()) && TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
usingDefaultRegAlloc()) usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57. // Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing()); addPass(createAArch64A57FPLoadBalancing());
return true;
} }
bool AArch64PassConfig::addPreSched2() { void AArch64PassConfig::addPreSched2() {
// Expand some pseudo instructions to allow proper scheduling. // Expand some pseudo instructions to allow proper scheduling.
addPass(createAArch64ExpandPseudoPass()); addPass(createAArch64ExpandPseudoPass(), false);
// Use load/store pair instructions when possible. // Use load/store pair instructions when possible.
if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt) if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass()); addPass(createAArch64LoadStoreOptimizationPass());
return true;
} }
bool AArch64PassConfig::addPreEmitPass() { void AArch64PassConfig::addPreEmitPass() {
if (EnableA53Fix835769) if (EnableA53Fix835769)
addPass(createAArch64A53Fix835769()); addPass(createAArch64A53Fix835769(), false);
// Relax conditional branch instructions if they're otherwise out of // Relax conditional branch instructions if they're otherwise out of
// range of their destination. // range of their destination.
addPass(createAArch64BranchRelaxation()); addPass(createAArch64BranchRelaxation(), false);
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH && if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
TM->getSubtarget<AArch64Subtarget>().isTargetMachO()) TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
addPass(createAArch64CollectLOHPass()); addPass(createAArch64CollectLOHPass());
return true;
} }

38
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -197,9 +197,9 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addPreISel() override; bool addPreISel() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreRegAlloc() override; void addPreRegAlloc() override;
bool addPreSched2() override; void addPreSched2() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -241,59 +241,53 @@ bool ARMPassConfig::addInstSelector() {
return false; return false;
} }
bool ARMPassConfig::addPreRegAlloc() { void ARMPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(createARMLoadStoreOptimizationPass(true)); addPass(createARMLoadStoreOptimizationPass(true), false);
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9()) if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
addPass(createMLxExpansionPass()); addPass(createMLxExpansionPass(), false);
// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
// enabled when NEON is available. // enabled when NEON is available.
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() && if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
getARMSubtarget().hasNEON() && !DisableA15SDOptimization) { getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
addPass(createA15SDOptimizerPass()); addPass(createA15SDOptimizerPass());
} }
return true;
} }
bool ARMPassConfig::addPreSched2() { void ARMPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
addPass(createARMLoadStoreOptimizationPass()); addPass(createARMLoadStoreOptimizationPass(), false);
printAndVerify("After ARM load / store optimizer");
if (getARMSubtarget().hasNEON()) if (getARMSubtarget().hasNEON())
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass)); addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass), false);
} }
// Expand some pseudo instructions into multiple instructions to allow // Expand some pseudo instructions into multiple instructions to allow
// proper scheduling. // proper scheduling.
addPass(createARMExpandPseudoPass()); addPass(createARMExpandPseudoPass(), false);
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) { if (!getARMSubtarget().isThumb1Only()) {
// in v8, IfConversion depends on Thumb instruction widths // in v8, IfConversion depends on Thumb instruction widths
if (getARMSubtarget().restrictIT() && if (getARMSubtarget().restrictIT() &&
!getARMSubtarget().prefers32BitThumb()) !getARMSubtarget().prefers32BitThumb())
addPass(createThumb2SizeReductionPass()); addPass(createThumb2SizeReductionPass(), false);
addPass(&IfConverterID); addPass(&IfConverterID, false);
} }
} }
if (getARMSubtarget().isThumb2()) if (getARMSubtarget().isThumb2())
addPass(createThumb2ITBlockPass()); addPass(createThumb2ITBlockPass());
return true;
} }
bool ARMPassConfig::addPreEmitPass() { void ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) { if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb()) if (!getARMSubtarget().prefers32BitThumb())
addPass(createThumb2SizeReductionPass()); addPass(createThumb2SizeReductionPass(), false);
// Constant island pass work on unbundled instructions. // Constant island pass work on unbundled instructions.
addPass(&UnpackMachineBundlesID); addPass(&UnpackMachineBundlesID, false);
} }
addPass(createARMOptimizeBarriersPass()); addPass(createARMOptimizeBarriersPass(), false);
addPass(createARMConstantIslandPass()); addPass(createARMConstantIslandPass());
return true;
} }

40
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -103,10 +103,10 @@ public:
} }
bool addInstSelector() override; bool addInstSelector() override;
bool addPreRegAlloc() override; void addPreRegAlloc() override;
bool addPostRegAlloc() override; void addPostRegAlloc() override;
bool addPreSched2() override; void addPreSched2() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -131,51 +131,45 @@ bool HexagonPassConfig::addInstSelector() {
return false; return false;
} }
bool HexagonPassConfig::addPreRegAlloc() { void HexagonPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
if (!DisableHardwareLoops) if (!DisableHardwareLoops)
addPass(createHexagonHardwareLoops()); addPass(createHexagonHardwareLoops(), false);
return false;
} }
bool HexagonPassConfig::addPostRegAlloc() { void HexagonPassConfig::addPostRegAlloc() {
const HexagonTargetMachine &TM = getHexagonTargetMachine(); const HexagonTargetMachine &TM = getHexagonTargetMachine();
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
if (!DisableHexagonCFGOpt) if (!DisableHexagonCFGOpt)
addPass(createHexagonCFGOptimizer(TM)); addPass(createHexagonCFGOptimizer(TM), false);
return false;
} }
bool HexagonPassConfig::addPreSched2() { void HexagonPassConfig::addPreSched2() {
const HexagonTargetMachine &TM = getHexagonTargetMachine(); const HexagonTargetMachine &TM = getHexagonTargetMachine();
addPass(createHexagonCopyToCombine()); addPass(createHexagonCopyToCombine(), false);
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID); addPass(&IfConverterID, false);
addPass(createHexagonSplitConst32AndConst64(TM)); addPass(createHexagonSplitConst32AndConst64(TM));
printAndVerify("After hexagon split const32/64 pass");
return true;
} }
bool HexagonPassConfig::addPreEmitPass() { void HexagonPassConfig::addPreEmitPass() {
const HexagonTargetMachine &TM = getHexagonTargetMachine(); const HexagonTargetMachine &TM = getHexagonTargetMachine();
bool NoOpt = (getOptLevel() == CodeGenOpt::None); bool NoOpt = (getOptLevel() == CodeGenOpt::None);
if (!NoOpt) if (!NoOpt)
addPass(createHexagonNewValueJump()); addPass(createHexagonNewValueJump(), false);
// Expand Spill code for predicate registers. // Expand Spill code for predicate registers.
addPass(createHexagonExpandPredSpillCode(TM)); addPass(createHexagonExpandPredSpillCode(TM), false);
// Split up TFRcondsets into conditional transfers. // Split up TFRcondsets into conditional transfers.
addPass(createHexagonSplitTFRCondSets(TM)); addPass(createHexagonSplitTFRCondSets(TM), false);
// Create Packets. // Create Packets.
if (!NoOpt) { if (!NoOpt) {
if (!DisableHardwareLoops) if (!DisableHardwareLoops)
addPass(createHexagonFixupHwLoops()); addPass(createHexagonFixupHwLoops(), false);
addPass(createHexagonPacketizer()); addPass(createHexagonPacketizer(), false);
} }
return false;
} }

7
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -50,7 +50,7 @@ public:
} }
bool addInstSelector() override; bool addInstSelector() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -64,8 +64,7 @@ bool MSP430PassConfig::addInstSelector() {
return false; return false;
} }
bool MSP430PassConfig::addPreEmitPass() { void MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer. // Must run branch selection immediately preceding the asm printer.
addPass(createMSP430BranchSelectionPass()); addPass(createMSP430BranchSelectionPass(), false);
return false;
} }

19
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -170,9 +170,9 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addInstSelector() override; bool addInstSelector() override;
void addMachineSSAOptimization() override; void addMachineSSAOptimization() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
bool addPreRegAlloc() override; void addPreRegAlloc() override;
}; };
} // namespace } // namespace
@ -203,13 +203,9 @@ void MipsPassConfig::addMachineSSAOptimization() {
TargetPassConfig::addMachineSSAOptimization(); TargetPassConfig::addMachineSSAOptimization();
} }
bool MipsPassConfig::addPreRegAlloc() { void MipsPassConfig::addPreRegAlloc() {
if (getOptLevel() == CodeGenOpt::None) { if (getOptLevel() == CodeGenOpt::None)
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine())); addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
return true;
}
else
return false;
} }
void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) { void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
@ -228,10 +224,9 @@ void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
// Implemented by targets that want to run passes immediately before // Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should // machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes. // print out the code after the passes.
bool MipsPassConfig::addPreEmitPass() { void MipsPassConfig::addPreEmitPass() {
MipsTargetMachine &TM = getMipsTargetMachine(); MipsTargetMachine &TM = getMipsTargetMachine();
addPass(createMipsDelaySlotFillerPass(TM)); addPass(createMipsDelaySlotFillerPass(TM), false);
addPass(createMipsLongBranchPass(TM)); addPass(createMipsLongBranchPass(TM), false);
addPass(createMipsConstantIslandPass(TM)); addPass(createMipsConstantIslandPass(TM));
return true;
} }

9
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -110,8 +110,7 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreRegAlloc() override; void addPostRegAlloc() override;
bool addPostRegAlloc() override;
void addMachineSSAOptimization() override; void addMachineSSAOptimization() override;
FunctionPass *createTargetRegisterAllocator(bool) override; FunctionPass *createTargetRegisterAllocator(bool) override;
@ -183,10 +182,8 @@ bool NVPTXPassConfig::addInstSelector() {
return false; return false;
} }
bool NVPTXPassConfig::addPreRegAlloc() { return false; } void NVPTXPassConfig::addPostRegAlloc() {
bool NVPTXPassConfig::addPostRegAlloc() { addPass(createNVPTXPrologEpilogPass(), false);
addPass(createNVPTXPrologEpilogPass());
return false;
} }
FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) { FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {

22
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -162,9 +162,9 @@ public:
bool addPreISel() override; bool addPreISel() override;
bool addILPOpts() override; bool addILPOpts() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreRegAlloc() override; void addPreRegAlloc() override;
bool addPreSched2() override; void addPreSched2() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -216,28 +216,24 @@ bool PPCPassConfig::addInstSelector() {
return false; return false;
} }
bool PPCPassConfig::addPreRegAlloc() { void PPCPassConfig::addPreRegAlloc() {
initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
&PPCVSXFMAMutateID); &PPCVSXFMAMutateID);
return false;
} }
bool PPCPassConfig::addPreSched2() { void PPCPassConfig::addPreSched2() {
addPass(createPPCVSXCopyCleanupPass()); addPass(createPPCVSXCopyCleanupPass(), false);
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID); addPass(&IfConverterID);
return true;
} }
bool PPCPassConfig::addPreEmitPass() { void PPCPassConfig::addPreEmitPass() {
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(createPPCEarlyReturnPass()); addPass(createPPCEarlyReturnPass(), false);
// Must run branch selection immediately preceding the asm printer. // Must run branch selection immediately preceding the asm printer.
addPass(createPPCBranchSelectionPass()); addPass(createPPCBranchSelectionPass(), false);
return false;
} }
void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) { void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {

47
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -87,10 +87,10 @@ public:
void addCodeGenPrepare() override; void addCodeGenPrepare() override;
bool addPreISel() override; bool addPreISel() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreRegAlloc() override; void addPreRegAlloc() override;
bool addPostRegAlloc() override; void addPostRegAlloc() override;
bool addPreSched2() override; void addPreSched2() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // End of anonymous namespace } // End of anonymous namespace
@ -163,7 +163,7 @@ bool AMDGPUPassConfig::addInstSelector() {
return false; return false;
} }
bool AMDGPUPassConfig::addPreRegAlloc() { void AMDGPUPassConfig::addPreRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
@ -179,47 +179,42 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID); insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
} }
addPass(createSIShrinkInstructionsPass()); addPass(createSIShrinkInstructionsPass(), false);
addPass(createSIFixSGPRLiveRangesPass()); addPass(createSIFixSGPRLiveRangesPass(), false);
} }
return false;
} }
bool AMDGPUPassConfig::addPostRegAlloc() { void AMDGPUPassConfig::addPostRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) { if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
addPass(createSIShrinkInstructionsPass()); addPass(createSIShrinkInstructionsPass(), false);
} }
return false;
} }
bool AMDGPUPassConfig::addPreSched2() { void AMDGPUPassConfig::addPreSched2() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
addPass(createR600EmitClauseMarkers()); addPass(createR600EmitClauseMarkers(), false);
if (ST.isIfCvtEnabled()) if (ST.isIfCvtEnabled())
addPass(&IfConverterID); addPass(&IfConverterID, false);
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
addPass(createR600ClauseMergePass(*TM)); addPass(createR600ClauseMergePass(*TM), false);
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
addPass(createSIInsertWaits(*TM)); addPass(createSIInsertWaits(*TM), false);
} }
return false;
} }
bool AMDGPUPassConfig::addPreEmitPass() { void AMDGPUPassConfig::addPreEmitPass() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
addPass(createAMDGPUCFGStructurizerPass()); addPass(createAMDGPUCFGStructurizerPass(), false);
addPass(createR600ExpandSpecialInstrsPass(*TM)); addPass(createR600ExpandSpecialInstrsPass(*TM), false);
addPass(&FinalizeMachineBundlesID); addPass(&FinalizeMachineBundlesID, false);
addPass(createR600Packetizer(*TM)); addPass(createR600Packetizer(*TM), false);
addPass(createR600ControlFlowFinalizer(*TM)); addPass(createR600ControlFlowFinalizer(*TM), false);
} else { } else {
addPass(createSILowerControlFlowPass(*TM)); addPass(createSILowerControlFlowPass(*TM), false);
} }
return false;
} }

8
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -53,7 +53,7 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -72,12 +72,8 @@ bool SparcPassConfig::addInstSelector() {
return false; return false;
} }
/// addPreEmitPass - This pass may be implemented by targets that want to run void SparcPassConfig::addPreEmitPass(){
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
bool SparcPassConfig::addPreEmitPass(){
addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
return true;
} }
void SparcV8TargetMachine::anchor() { } void SparcV8TargetMachine::anchor() { }

14
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -46,8 +46,8 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreSched2() override; void addPreSched2() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // end anonymous namespace } // end anonymous namespace
@ -60,14 +60,13 @@ bool SystemZPassConfig::addInstSelector() {
return false; return false;
} }
bool SystemZPassConfig::addPreSched2() { void SystemZPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None && if (getOptLevel() != CodeGenOpt::None &&
getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond()) getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
addPass(&IfConverterID); addPass(&IfConverterID);
return true;
} }
bool SystemZPassConfig::addPreEmitPass() { void SystemZPassConfig::addPreEmitPass() {
// We eliminate comparisons here rather than earlier because some // We eliminate comparisons here rather than earlier because some
// transformations can change the set of available CC values and we // transformations can change the set of available CC values and we
// generally want those transformations to have priority. This is // generally want those transformations to have priority. This is
@ -92,11 +91,10 @@ bool SystemZPassConfig::addPreEmitPass() {
// between the comparison and the branch, but it isn't clear whether // between the comparison and the branch, but it isn't clear whether
// preventing that would be a win or not. // preventing that would be a win or not.
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZElimComparePass(getSystemZTargetMachine())); addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZShortenInstPass(getSystemZTargetMachine())); addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
return true;
} }
TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {

32
lib/Target/X86/X86TargetMachine.cpp
View File

@ -154,9 +154,8 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addILPOpts() override; bool addILPOpts() override;
bool addPreRegAlloc() override; void addPostRegAlloc() override;
bool addPostRegAlloc() override; void addPreEmitPass() override;
bool addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -188,32 +187,19 @@ bool X86PassConfig::addILPOpts() {
return true; return true;
} }
bool X86PassConfig::addPreRegAlloc() { void X86PassConfig::addPostRegAlloc() {
return false; // -print-machineinstr shouldn't print after this.
}
bool X86PassConfig::addPostRegAlloc() {
addPass(createX86FloatingPointStackifierPass()); addPass(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
} }
bool X86PassConfig::addPreEmitPass() { void X86PassConfig::addPreEmitPass() {
bool ShouldPrint = false; if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2())
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { addPass(createExecutionDependencyFixPass(&X86::VR128RegClass), false);
addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true;
}
if (UseVZeroUpper) { if (UseVZeroUpper)
addPass(createX86IssueVZeroUpperPass()); addPass(createX86IssueVZeroUpperPass(), false);
ShouldPrint = true;
}
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
addPass(createX86PadShortFunctions()); addPass(createX86PadShortFunctions(), false);
addPass(createX86FixupLEAs()); addPass(createX86FixupLEAs());
ShouldPrint = true;
} }
return ShouldPrint;
} }

7
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -48,7 +48,7 @@ public:
void addIRPasses() override; void addIRPasses() override;
bool addPreISel() override; bool addPreISel() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addPreEmitPass() override; void addPreEmitPass() override;
}; };
} // namespace } // namespace
@ -72,9 +72,8 @@ bool XCorePassConfig::addInstSelector() {
return false; return false;
} }
bool XCorePassConfig::addPreEmitPass() { void XCorePassConfig::addPreEmitPass() {
addPass(createXCoreFrameToArgsOffsetEliminationPass()); addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
return false;
} }
// Force static initialization. // Force static initialization.