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[SystemZ] Use RNSBG
This should be the last of the R.SBG patches for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186573 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
6a3d933e16
commit
722a26d63e
@ -118,11 +118,6 @@ such as ICM and STCM.
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--
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We could make more use of the ROTATE AND ... SELECTED BITS instructions.
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At the moment we only use RISBG, and only then for subword atomic operations.
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--
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DAGCombiner can detect integer absolute, but there's not yet an associated
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ISD opcode. We could add one and implement it using LOAD POSITIVE.
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Negated absolutes could use LOAD NEGATIVE.
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@ -97,15 +97,24 @@ static uint64_t allOnes(unsigned int Count) {
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return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
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}
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// Represents operands 2 to 5 of a ROTATE AND ... SELECTED BITS operation.
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// The operands are: Input (R2), Start (I3), End (I4) and Rotate (I5).
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// The operand value is effectively (and (rotl Input Rotate) Mask) and
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// has BitSize bits.
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// Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
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// given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
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// Rotate (I5). The combined operand value is effectively:
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//
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// (or (rotl Input, Rotate), ~Mask)
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//
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// for RNSBG and:
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//
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// (and (rotl Input, Rotate), Mask)
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//
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// otherwise. The value has BitSize bits.
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struct RxSBGOperands {
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RxSBGOperands(SDValue N)
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: BitSize(N.getValueType().getSizeInBits()), Mask(allOnes(BitSize)),
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Input(N), Start(64 - BitSize), End(63), Rotate(0) {}
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RxSBGOperands(unsigned Op, SDValue N)
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: Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
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Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
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Rotate(0) {}
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unsigned Opcode;
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unsigned BitSize;
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uint64_t Mask;
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SDValue Input;
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@ -671,6 +680,9 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) {
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unsigned Opcode = N.getOpcode();
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switch (Opcode) {
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case ISD::AND: {
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if (RxSBG.Opcode == SystemZ::RNSBG)
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return false;
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ConstantSDNode *MaskNode =
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dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
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if (!MaskNode)
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@ -692,6 +704,31 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) {
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return true;
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}
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case ISD::OR: {
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if (RxSBG.Opcode != SystemZ::RNSBG)
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return false;
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ConstantSDNode *MaskNode =
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dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
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if (!MaskNode)
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return false;
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SDValue Input = N.getOperand(0);
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uint64_t Mask = ~MaskNode->getZExtValue();
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if (!refineRxSBGMask(RxSBG, Mask)) {
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// If some bits of Input are already known ones, those bits will have
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// been removed from the mask. See if adding them back in makes the
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// mask suitable.
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APInt KnownZero, KnownOne;
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CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
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Mask &= ~KnownOne.getZExtValue();
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if (!refineRxSBGMask(RxSBG, Mask))
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return false;
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}
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RxSBG.Input = Input;
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return true;
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}
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case ISD::ROTL: {
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// Any 64-bit rotate left can be merged into the RxSBG.
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if (RxSBG.BitSize != 64)
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@ -707,18 +744,26 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) {
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}
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case ISD::SHL: {
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// Treat (shl X, count) as (and (rotl X, count), ~0<<count).
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ConstantSDNode *CountNode =
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dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
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if (!CountNode)
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return false;
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uint64_t Count = CountNode->getZExtValue();
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if (Count < 1 ||
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Count >= RxSBG.BitSize ||
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!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count) << Count))
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if (Count < 1 || Count >= RxSBG.BitSize)
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return false;
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if (RxSBG.Opcode == SystemZ::RNSBG) {
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// Treat (shl X, count) as (rotl X, size-count) as long as the bottom
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// count bits from RxSBG.Input are ignored.
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if (shiftedInBitsMatter(RxSBG, Count, true))
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return false;
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} else {
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// Treat (shl X, count) as (and (rotl X, count), ~0<<count).
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if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count) << Count))
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return false;
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}
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RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
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RxSBG.Input = N.getOperand(0);
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return true;
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@ -735,9 +780,9 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) {
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if (Count < 1 || Count >= RxSBG.BitSize)
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return false;
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if (Opcode == ISD::SRA) {
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// Treat (sra X, count) as (rotl X, size-count) as long as the top
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// Count bits from RxSBG.Input are ignored.
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if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
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// Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
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// count bits from RxSBG.Input are ignored.
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if (shiftedInBitsMatter(RxSBG, Count, false))
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return false;
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} else {
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@ -779,7 +824,7 @@ SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) {
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}
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SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
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RxSBGOperands RISBG(SDValue(N, 0));
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RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
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unsigned Count = 0;
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while (expandRxSBG(RISBG))
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Count += 1;
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@ -811,7 +856,10 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
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SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
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// Try treating each operand of N as the second operand of the RxSBG
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// and see which goes deepest.
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RxSBGOperands RxSBG[] = { N->getOperand(0), N->getOperand(1) };
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RxSBGOperands RxSBG[] = {
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RxSBGOperands(Opcode, N->getOperand(0)),
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RxSBGOperands(Opcode, N->getOperand(1))
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};
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unsigned Count[] = { 0, 0 };
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for (unsigned I = 0; I < 2; ++I)
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while (expandRxSBG(RxSBG[I]))
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@ -941,6 +989,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
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break;
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case ISD::AND:
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if (Node->getOperand(1).getOpcode() != ISD::Constant)
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ResNode = tryRxSBG(Node, SystemZ::RNSBG);
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// Fall through.
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case ISD::ROTL:
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case ISD::SHL:
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case ISD::SRL:
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257
test/CodeGen/SystemZ/rnsbg-01.ll
Normal file
257
test/CodeGen/SystemZ/rnsbg-01.ll
Normal file
@ -0,0 +1,257 @@
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; Test sequences that can use RNSBG.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test a simple mask, which is a wrap-around case.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: rnsbg %r2, %r3, 59, 56, 0
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; CHECK: br %r14
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%orb = or i32 %b, 96
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: rnsbg %r2, %r3, 59, 56, 0
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; CHECK: br %r14
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%orb = or i64 %b, 96
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case where no wraparound is needed.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: rnsbg %r2, %r3, 58, 61, 0
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; CHECK: br %r14
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%orb = or i32 %b, -61
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: rnsbg %r2, %r3, 58, 61, 0
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; CHECK: br %r14
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%orb = or i64 %b, -61
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with just a left shift. This can't use RNSBG.
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define i32 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: sll {{%r[0-5]}}
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; CHECK: nr {{%r[0-5]}}
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; CHECK: br %r14
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%shrb = shl i32 %b, 20
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%and = and i32 %a, %shrb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f7(i64 %a, i64 %b) {
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; CHECK-LABEL: f7:
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; CHECK: sllg {{%r[0-5]}}
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; CHECK: ngr {{%r[0-5]}}
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; CHECK: br %r14
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%shrb = shl i64 %b, 20
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%and = and i64 %a, %shrb
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ret i64 %and
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}
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; Test a case with just a rotate. This can't use RNSBG.
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define i32 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: rll {{%r[0-5]}}
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; CHECK: nr {{%r[0-5]}}
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; CHECK: br %r14
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%shlb = shl i32 %b, 22
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%shrb = lshr i32 %b, 10
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%rotlb = or i32 %shlb, %shrb
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%and = and i32 %a, %rotlb
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ret i32 %and
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}
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; ...and again with i64, which can.
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define i64 @f9(i64 %a, i64 %b) {
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; CHECK-LABEL: f9:
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; CHECK: rnsbg %r2, %r3, 0, 63, 44
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; CHECK: br %r14
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%shlb = shl i64 %b, 44
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%shrb = lshr i64 %b, 20
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%rotlb = or i64 %shlb, %shrb
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%and = and i64 %a, %rotlb
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ret i64 %and
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}
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; Test a case with a left shift and OR, where the OR covers all shifted bits.
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; We can do the whole thing using RNSBG.
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: rnsbg %r2, %r3, 32, 56, 7
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; CHECK: br %r14
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%shlb = shl i32 %b, 7
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%orb = or i32 %shlb, 127
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f11(i64 %a, i64 %b) {
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; CHECK-LABEL: f11:
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; CHECK: rnsbg %r2, %r3, 0, 56, 7
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; CHECK: br %r14
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%shlb = shl i64 %b, 7
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%orb = or i64 %shlb, 127
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a left shift and OR, where the OR doesn't cover all
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; shifted bits. We can't use RNSBG for the shift, but we can for the OR
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; and AND.
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define i32 @f12(i32 %a, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: sll %r3, 7
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; CHECK: rnsbg %r2, %r3, 32, 57, 0
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; CHECK: br %r14
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%shlb = shl i32 %b, 7
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%orb = or i32 %shlb, 63
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f13(i64 %a, i64 %b) {
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; CHECK-LABEL: f13:
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; CHECK: sllg [[REG:%r[01345]]], %r3, 7
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; CHECK: rnsbg %r2, [[REG]], 0, 57, 0
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; CHECK: br %r14
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%shlb = shl i64 %b, 7
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%orb = or i64 %shlb, 63
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a right shift and OR, where the OR covers all the shifted
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; bits. The whole thing can be done using RNSBG.
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define i32 @f14(i32 %a, i32 %b) {
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; CHECK-LABEL: f14:
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; CHECK: rnsbg %r2, %r3, 60, 63, 37
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; CHECK: br %r14
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%shrb = lshr i32 %b, 27
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%orb = or i32 %shrb, -16
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f15(i64 %a, i64 %b) {
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; CHECK-LABEL: f15:
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; CHECK: rnsbg %r2, %r3, 60, 63, 5
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; CHECK: br %r14
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%shrb = lshr i64 %b, 59
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%orb = or i64 %shrb, -16
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a right shift and OR, where the OR doesn't cover all the
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; shifted bits. The shift needs to be done separately, but the OR and AND
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; can use RNSBG.
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define i32 @f16(i32 %a, i32 %b) {
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; CHECK-LABEL: f16:
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; CHECK: srl %r3, 29
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; CHECK: rnsbg %r2, %r3, 60, 63, 0
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; CHECK: br %r14
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%shrb = lshr i32 %b, 29
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%orb = or i32 %shrb, -16
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f17(i64 %a, i64 %b) {
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; CHECK-LABEL: f17:
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; CHECK: srlg [[REG:%r[01345]]], %r3, 61
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; CHECK: rnsbg %r2, [[REG]], 60, 63, 0
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; CHECK: br %r14
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%shrb = lshr i64 %b, 61
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%orb = or i64 %shrb, -16
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a combination involving an ASHR in which the sign bits matter.
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; We can't use RNSBG for the ASHR in that case, but we can for the rest.
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define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f18:
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; CHECK: sra %r3, 4
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; CHECK: rnsbg %r2, %r3, 32, 62, 1
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; CHECK: br %r14
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%ashrb = ashr i32 %b, 4
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store i32 %ashrb, i32 *%dest
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%shlb = shl i32 %ashrb, 1
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%orb = or i32 %shlb, 1
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f19:
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; CHECK: srag [[REG:%r[0145]]], %r3, 34
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; CHECK: rnsbg %r2, [[REG]], 0, 62, 1
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; CHECK: br %r14
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%ashrb = ashr i64 %b, 34
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store i64 %ashrb, i64 *%dest
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%shlb = shl i64 %ashrb, 1
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%orb = or i64 %shlb, 1
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a combination involving an ASHR in which the sign bits don't matter.
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define i32 @f20(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f20:
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; CHECK: rnsbg %r2, %r3, 48, 62, 48
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; CHECK: br %r14
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%ashrb = ashr i32 %b, 17
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store i32 %ashrb, i32 *%dest
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%shlb = shl i32 %ashrb, 1
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%orb = or i32 %shlb, -65535
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f21(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f21:
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; CHECK: rnsbg %r2, %r3, 48, 62, 16
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; CHECK: br %r14
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%ashrb = ashr i64 %b, 49
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store i64 %ashrb, i64 *%dest
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%shlb = shl i64 %ashrb, 1
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%orb = or i64 %shlb, -65535
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
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define i64 @f22(i64 %a, i64 %b) {
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; CHECK-LABEL: f22:
|
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; CHECK: rnsbg %r2, %r3, 60, 54, 9
|
||||
; CHECK: br %r14
|
||||
%shlb = shl i64 %b, 5
|
||||
%orb = or i64 %shlb, 31
|
||||
%shlorb = shl i64 %orb, 4
|
||||
%shrorb = lshr i64 %orb, 60
|
||||
%rotlorb = or i64 %shlorb, %shrorb
|
||||
%and = and i64 %a, %rotlorb
|
||||
ret i64 %and
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user