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Basic 64-bit ALU operations.

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SPARC v9 extends all ALU instructions to 64 bits, so we simply need to
add patterns to use them for both i32 and i64 values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-04-02 04:09:23 +00:00
parent 39e75544dc
commit 73c5f80ec9
2 changed files with 59 additions and 0 deletions
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38
lib/Target/Sparc/SparcInstr64Bit.td
View File

@ -133,3 +133,41 @@ def : Pat<(i64 imm:$val),
(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
(ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
Requires<[Is64Bit]>;
//===----------------------------------------------------------------------===//
// 64-bit Integer Arithmetic and Logic.
//===----------------------------------------------------------------------===//
let Predicates = [Is64Bit] in {
// Register-register instructions.
def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>;
def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
def : Pat<(or i64:$a, (not i64:$b)), (ORNrr $a, $b)>;
def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
// Add/sub with carry were renamed to addc/subc in SPARC v9.
def : Pat<(adde i64:$a, i64:$b), (ADDXrr $a, $b)>;
def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
// Register-immediate instructions.
def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>;
def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
} // Predicates = [Is64Bit]

21
test/CodeGen/SPARC/64bit.ll
View File

@ -65,3 +65,24 @@ define i64 @ret_nimm33() {
define i64 @ret_bigimm() {
ret i64 6800754272627607872
}
; CHECK: reg_reg_alu
; CHECK: add %i0, %i1, [[R0:%[goli][0-7]]]
; CHECK: sub [[R0]], %i2, [[R1:%[goli][0-7]]]
; CHECK: andn [[R1]], %i0, %i0
define i64 @reg_reg_alu(i64 %x, i64 %y, i64 %z) {
%a = add i64 %x, %y
%b = sub i64 %a, %z
%c = xor i64 %x, -1
%d = and i64 %b, %c
ret i64 %d
}
; CHECK: reg_imm_alu
; CHECK: add %i0, -5, [[R0:%[goli][0-7]]]
; CHECK: xor [[R0]], 2, %i0
define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
%a = add i64 %x, -5
%b = xor i64 %a, 2
ret i64 %b
}