mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Shrinkify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25837 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
273d463bef
commit
749d6fadf8
@ -43,6 +43,11 @@ def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def simm11 : PatLeaf<(imm), [{
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// simm11 predicate - True if the imm fits in a 11-bit sign extended field.
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return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
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}]>;
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def simm13 : PatLeaf<(imm), [{
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// simm13 predicate - True if the imm fits in a 13-bit sign extended field.
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return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
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@ -127,35 +132,41 @@ def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
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// Note that these values must be kept in sync with the V8CC::CondCode enum
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// values.
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def ICC_NE : PatLeaf<(i32 9)>; // Not Equal
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def ICC_E : PatLeaf<(i32 1)>; // Equal
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def ICC_G : PatLeaf<(i32 10)>; // Greater
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def ICC_LE : PatLeaf<(i32 2)>; // Less or Equal
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def ICC_GE : PatLeaf<(i32 11)>; // Greater or Equal
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def ICC_L : PatLeaf<(i32 3)>; // Less
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def ICC_GU : PatLeaf<(i32 12)>; // Greater Unsigned
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def ICC_LEU : PatLeaf<(i32 4)>; // Less or Equal Unsigned
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def ICC_CC : PatLeaf<(i32 13)>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : PatLeaf<(i32 5)>; // Carry Set/Less Unsigned
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def ICC_POS : PatLeaf<(i32 14)>; // Positive
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def ICC_NEG : PatLeaf<(i32 6)>; // Negative
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def ICC_VC : PatLeaf<(i32 15)>; // Overflow Clear
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def ICC_VS : PatLeaf<(i32 7)>; // Overflow Set
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class ICC_VAL<int N> : PatLeaf<(i32 N)> {
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int ICCVal = N;
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}
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def ICC_NE : ICC_VAL< 9>; // Not Equal
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def ICC_E : ICC_VAL< 1>; // Equal
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def ICC_G : ICC_VAL<10>; // Greater
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def ICC_LE : ICC_VAL< 2>; // Less or Equal
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def ICC_GE : ICC_VAL<11>; // Greater or Equal
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def ICC_L : ICC_VAL< 3>; // Less
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def ICC_GU : ICC_VAL<12>; // Greater Unsigned
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def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
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def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
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def ICC_POS : ICC_VAL<14>; // Positive
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def ICC_NEG : ICC_VAL< 6>; // Negative
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def ICC_VC : ICC_VAL<15>; // Overflow Clear
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def ICC_VS : ICC_VAL< 7>; // Overflow Set
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def FCC_U : PatLeaf<(i32 23)>; // Unordered
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def FCC_G : PatLeaf<(i32 22)>; // Greater
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def FCC_UG : PatLeaf<(i32 21)>; // Unordered or Greater
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def FCC_L : PatLeaf<(i32 20)>; // Less
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def FCC_UL : PatLeaf<(i32 19)>; // Unordered or Less
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def FCC_LG : PatLeaf<(i32 18)>; // Less or Greater
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def FCC_NE : PatLeaf<(i32 17)>; // Not Equal
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def FCC_E : PatLeaf<(i32 25)>; // Equal
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def FCC_UE : PatLeaf<(i32 24)>; // Unordered or Equal
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def FCC_GE : PatLeaf<(i32 25)>; // Greater or Equal
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def FCC_UGE : PatLeaf<(i32 26)>; // Unordered or Greater or Equal
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def FCC_LE : PatLeaf<(i32 27)>; // Less or Equal
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def FCC_ULE : PatLeaf<(i32 28)>; // Unordered or Less or Equal
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def FCC_O : PatLeaf<(i32 29)>; // Ordered
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class FCC_VAL<int N> : PatLeaf<(i32 N)> {
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int FCCVal = N;
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}
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def FCC_U : FCC_VAL<23>; // Unordered
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def FCC_G : FCC_VAL<22>; // Greater
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def FCC_UG : FCC_VAL<21>; // Unordered or Greater
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def FCC_L : FCC_VAL<20>; // Less
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def FCC_UL : FCC_VAL<19>; // Unordered or Less
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def FCC_LG : FCC_VAL<18>; // Less or Greater
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def FCC_NE : FCC_VAL<17>; // Not Equal
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def FCC_E : FCC_VAL<25>; // Equal
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def FCC_UE : FCC_VAL<24>; // Unordered or Equal
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def FCC_GE : FCC_VAL<25>; // Greater or Equal
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def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
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def FCC_LE : FCC_VAL<27>; // Less or Equal
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def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
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def FCC_O : FCC_VAL<29>; // Ordered
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//===----------------------------------------------------------------------===//
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@ -790,122 +801,54 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
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// V9 Conditional Moves.
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let Predicates = [HasV9], isTwoAddress = 1 in {
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// FIXME: Add instruction encodings for the JIT some day.
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// FIXME: Allow regalloc of the condition code some day.
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class IntCMOVICCrr<string asmstr, ICC_VAL CC>
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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asmstr,
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
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int CondBits = CC.ICCVal;
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}
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// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
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def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movne %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_NE, ICC))]>;
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def MOVE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"move %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_E, ICC))]>;
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def MOVG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movg %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_G, ICC))]>;
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def MOVLE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movle %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_LE, ICC))]>;
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def MOVGE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movge %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_GE, ICC))]>;
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def MOVL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movl %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_L, ICC))]>;
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def MOVGU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movgu %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_GU, ICC))]>;
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def MOVLEU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movleu %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_LEU, ICC))]>;
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def MOVCC : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movcc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_CC, ICC))]>;
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def MOVCS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movcs %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_CS, ICC))]>;
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def MOVPOS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movpos %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_POS, ICC))]>;
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def MOVNEG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movneg %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_NEG, ICC))]>;
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def MOVVC : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movvc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_VC, ICC))]>;
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def MOVVS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movvs %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, ICC_CS, ICC))]>;
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def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
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def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
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def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
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def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>;
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def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>;
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def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>;
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def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>;
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def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>;
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def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>;
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def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>;
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def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>;
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def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
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def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
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def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
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def MOVFU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfu %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_U, FCC))]>;
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def MOVFG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfg %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_G, FCC))]>;
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def MOVFUG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfug %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UG, FCC))]>;
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def MOVFL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfl %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_L, FCC))]>;
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def MOVFUL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movful %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UL, FCC))]>;
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def MOVFLG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movflg %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_LG, FCC))]>;
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def MOVFNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfne %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_NE, FCC))]>;
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def MOVFE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfe %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_E, FCC))]>;
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def MOVFUE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfue %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UE, FCC))]>;
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def MOVFGE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfge %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_GE, FCC))]>;
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def MOVFUGE: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfuge %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UGE, FCC))]>;
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def MOVFLE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfle %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_LE, FCC))]>;
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def MOVFULE: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfule %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_ULE, FCC))]>;
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def MOVFO : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movfo %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_O, FCC))]>;
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// FIXME: Allow regalloc of the fcc condition code some day.
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class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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asmstr,
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[(set IntRegs:$dst,
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(V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
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int CondBits = CC.FCCVal;
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}
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def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
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def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
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def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
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def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>;
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def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>;
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def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>;
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def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>;
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def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>;
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def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>;
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def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>;
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def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>;
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def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
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def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
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def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
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}
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// Floating-Point Move Instructions, p. 164 of the V9 manual.
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@ -43,6 +43,11 @@ def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def simm11 : PatLeaf<(imm), [{
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// simm11 predicate - True if the imm fits in a 11-bit sign extended field.
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return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
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}]>;
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def simm13 : PatLeaf<(imm), [{
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// simm13 predicate - True if the imm fits in a 13-bit sign extended field.
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return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
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@ -127,35 +132,41 @@ def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
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// Note that these values must be kept in sync with the V8CC::CondCode enum
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// values.
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def ICC_NE : PatLeaf<(i32 9)>; // Not Equal
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def ICC_E : PatLeaf<(i32 1)>; // Equal
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def ICC_G : PatLeaf<(i32 10)>; // Greater
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def ICC_LE : PatLeaf<(i32 2)>; // Less or Equal
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def ICC_GE : PatLeaf<(i32 11)>; // Greater or Equal
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def ICC_L : PatLeaf<(i32 3)>; // Less
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def ICC_GU : PatLeaf<(i32 12)>; // Greater Unsigned
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def ICC_LEU : PatLeaf<(i32 4)>; // Less or Equal Unsigned
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def ICC_CC : PatLeaf<(i32 13)>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : PatLeaf<(i32 5)>; // Carry Set/Less Unsigned
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def ICC_POS : PatLeaf<(i32 14)>; // Positive
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def ICC_NEG : PatLeaf<(i32 6)>; // Negative
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def ICC_VC : PatLeaf<(i32 15)>; // Overflow Clear
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def ICC_VS : PatLeaf<(i32 7)>; // Overflow Set
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class ICC_VAL<int N> : PatLeaf<(i32 N)> {
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int ICCVal = N;
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}
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def ICC_NE : ICC_VAL< 9>; // Not Equal
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def ICC_E : ICC_VAL< 1>; // Equal
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def ICC_G : ICC_VAL<10>; // Greater
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def ICC_LE : ICC_VAL< 2>; // Less or Equal
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def ICC_GE : ICC_VAL<11>; // Greater or Equal
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def ICC_L : ICC_VAL< 3>; // Less
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def ICC_GU : ICC_VAL<12>; // Greater Unsigned
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def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
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def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
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def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
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def ICC_POS : ICC_VAL<14>; // Positive
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def ICC_NEG : ICC_VAL< 6>; // Negative
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def ICC_VC : ICC_VAL<15>; // Overflow Clear
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def ICC_VS : ICC_VAL< 7>; // Overflow Set
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def FCC_U : PatLeaf<(i32 23)>; // Unordered
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def FCC_G : PatLeaf<(i32 22)>; // Greater
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def FCC_UG : PatLeaf<(i32 21)>; // Unordered or Greater
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def FCC_L : PatLeaf<(i32 20)>; // Less
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def FCC_UL : PatLeaf<(i32 19)>; // Unordered or Less
|
||||
def FCC_LG : PatLeaf<(i32 18)>; // Less or Greater
|
||||
def FCC_NE : PatLeaf<(i32 17)>; // Not Equal
|
||||
def FCC_E : PatLeaf<(i32 25)>; // Equal
|
||||
def FCC_UE : PatLeaf<(i32 24)>; // Unordered or Equal
|
||||
def FCC_GE : PatLeaf<(i32 25)>; // Greater or Equal
|
||||
def FCC_UGE : PatLeaf<(i32 26)>; // Unordered or Greater or Equal
|
||||
def FCC_LE : PatLeaf<(i32 27)>; // Less or Equal
|
||||
def FCC_ULE : PatLeaf<(i32 28)>; // Unordered or Less or Equal
|
||||
def FCC_O : PatLeaf<(i32 29)>; // Ordered
|
||||
class FCC_VAL<int N> : PatLeaf<(i32 N)> {
|
||||
int FCCVal = N;
|
||||
}
|
||||
def FCC_U : FCC_VAL<23>; // Unordered
|
||||
def FCC_G : FCC_VAL<22>; // Greater
|
||||
def FCC_UG : FCC_VAL<21>; // Unordered or Greater
|
||||
def FCC_L : FCC_VAL<20>; // Less
|
||||
def FCC_UL : FCC_VAL<19>; // Unordered or Less
|
||||
def FCC_LG : FCC_VAL<18>; // Less or Greater
|
||||
def FCC_NE : FCC_VAL<17>; // Not Equal
|
||||
def FCC_E : FCC_VAL<25>; // Equal
|
||||
def FCC_UE : FCC_VAL<24>; // Unordered or Equal
|
||||
def FCC_GE : FCC_VAL<25>; // Greater or Equal
|
||||
def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
|
||||
def FCC_LE : FCC_VAL<27>; // Less or Equal
|
||||
def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
|
||||
def FCC_O : FCC_VAL<29>; // Ordered
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -790,122 +801,54 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
||||
// V9 Conditional Moves.
|
||||
let Predicates = [HasV9], isTwoAddress = 1 in {
|
||||
// FIXME: Add instruction encodings for the JIT some day.
|
||||
// FIXME: Allow regalloc of the condition code some day.
|
||||
class IntCMOVICCrr<string asmstr, ICC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
|
||||
int CondBits = CC.ICCVal;
|
||||
}
|
||||
|
||||
|
||||
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
|
||||
def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movne %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_NE, ICC))]>;
|
||||
def MOVE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"move %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_E, ICC))]>;
|
||||
def MOVG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movg %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_G, ICC))]>;
|
||||
def MOVLE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movle %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_LE, ICC))]>;
|
||||
def MOVGE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movge %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_GE, ICC))]>;
|
||||
def MOVL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movl %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_L, ICC))]>;
|
||||
def MOVGU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movgu %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_GU, ICC))]>;
|
||||
def MOVLEU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movleu %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_LEU, ICC))]>;
|
||||
def MOVCC : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movcc %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_CC, ICC))]>;
|
||||
def MOVCS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movcs %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_CS, ICC))]>;
|
||||
def MOVPOS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movpos %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_POS, ICC))]>;
|
||||
def MOVNEG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movneg %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_NEG, ICC))]>;
|
||||
def MOVVC : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movvc %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_VC, ICC))]>;
|
||||
def MOVVS : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movvs %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selecticc IntRegs:$F, IntRegs:$T, ICC_CS, ICC))]>;
|
||||
def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
|
||||
def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
|
||||
def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
|
||||
def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>;
|
||||
def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>;
|
||||
def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>;
|
||||
def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>;
|
||||
def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>;
|
||||
def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>;
|
||||
def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>;
|
||||
def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>;
|
||||
def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
|
||||
def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
|
||||
def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
|
||||
|
||||
def MOVFU : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfu %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_U, FCC))]>;
|
||||
def MOVFG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfg %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_G, FCC))]>;
|
||||
def MOVFUG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfug %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UG, FCC))]>;
|
||||
def MOVFL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfl %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_L, FCC))]>;
|
||||
def MOVFUL : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movful %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UL, FCC))]>;
|
||||
def MOVFLG : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movflg %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_LG, FCC))]>;
|
||||
def MOVFNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfne %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_NE, FCC))]>;
|
||||
def MOVFE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfe %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_E, FCC))]>;
|
||||
def MOVFUE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfue %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UE, FCC))]>;
|
||||
def MOVFGE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfge %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_GE, FCC))]>;
|
||||
def MOVFUGE: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfuge %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_UGE, FCC))]>;
|
||||
def MOVFLE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfle %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_LE, FCC))]>;
|
||||
def MOVFULE: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfule %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_ULE, FCC))]>;
|
||||
def MOVFO : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
"movfo %fcc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, FCC_O, FCC))]>;
|
||||
// FIXME: Allow regalloc of the fcc condition code some day.
|
||||
class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
|
||||
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
|
||||
asmstr,
|
||||
[(set IntRegs:$dst,
|
||||
(V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
|
||||
int CondBits = CC.FCCVal;
|
||||
}
|
||||
|
||||
def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
|
||||
def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
|
||||
def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
|
||||
def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>;
|
||||
def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>;
|
||||
def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>;
|
||||
def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>;
|
||||
def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>;
|
||||
def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>;
|
||||
def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>;
|
||||
def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>;
|
||||
def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
|
||||
def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
|
||||
def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
|
||||
}
|
||||
|
||||
// Floating-Point Move Instructions, p. 164 of the V9 manual.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user