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Generate dummy Phi machine instruction, plus a bug fix for BrCond(boolreg).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -138,7 +138,8 @@ ThisIsAChainRule(int eruleno)
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case 130:
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case 131:
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case 132:
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case 153: return true; break;
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case 153:
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case 155: return true; break;
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default: return false; break;
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}
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@ -310,7 +311,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 27: // reg: ToUIntTy(reg)
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case 29: // reg: ToULongTy(reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || opType == Type::BoolTy);
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assert(opType->isIntegral() ||
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opType->isPointerType() ||
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opType == Type::BoolTy && "Ignoring cast: illegal for other types");
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numInstr = 0;
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forwardOperandNum = 0;
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break;
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@ -534,6 +537,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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case 43: // boolreg: VReg
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case 44: // boolreg: Constant
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numInstr = 0;
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break;
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@ -709,6 +713,17 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 64: // reg: Phi(reg,reg)
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{ // This instruction has variable #operands, so resultPos is 0.
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Instruction* phi = subtreeRoot->getInstruction();
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mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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subtreeRoot->getValue());
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for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
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mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
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phi->getOperand(i));
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break;
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}
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case 71: // reg: VReg
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case 72: // reg: Constant
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numInstr = 0; // don't forward the value
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@ -730,6 +745,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 131:
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case 132:
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case 153:
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case 155:
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//
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// These are all chain rules, which have a single nonterminal on the RHS.
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// Get the rule that matches the RHS non-terminal and use that instead.
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@ -1418,7 +1434,7 @@ FixConstantOperands(const InstructionNode* vmInstrNode,
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const MachineInstrDescriptor& instrDesc =
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target.getInstrInfo().getDescriptor(minstr->getOpCode());
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for (unsigned op=0; op < instrDesc.numOperands; op++)
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for (unsigned op=0; op < minstr->getNumOperands(); op++)
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{
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const MachineOperand& mop = minstr->getOperand(op);
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