mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
2f70f1a1d8
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753480ad20
@ -614,15 +614,17 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
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return false;
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if (TID.getNumDefs() != 1)
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return false;
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// Make sure the copy destination register class fits the instruction
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// definition register class. The mismatch can happen as a result of earlier
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// extract_subreg, insert_subreg, subreg_to_reg coalescing.
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const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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if (mri_->getRegClass(DstReg) != RC)
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if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
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// Make sure the copy destination register class fits the instruction
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// definition register class. The mismatch can happen as a result of earlier
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// extract_subreg, insert_subreg, subreg_to_reg coalescing.
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const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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if (mri_->getRegClass(DstReg) != RC)
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return false;
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} else if (!RC->contains(DstReg))
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return false;
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} else if (!RC->contains(DstReg))
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return false;
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}
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unsigned DefIdx = li_->getDefIndex(CopyIdx);
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const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
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@ -1378,13 +1380,17 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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}
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}
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if (SubIdx) {
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if (isInsSubReg || isSubRegToReg) {
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if (!DstIsPhys && !SrcIsPhys) {
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if (!DstIsPhys && !SrcIsPhys) {
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if (isInsSubReg || isSubRegToReg) {
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NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
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if (!NewRC)
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return false;
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} else // extract_subreg {
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NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
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}
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if (!NewRC) {
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DOUT << "\t Conflicting sub-register indices.\n";
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return false; // Not coalescable
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}
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unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
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unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
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unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
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@ -161,69 +161,84 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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case 1:
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// 8-bit
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if (B == &X86::GR8RegClass) {
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if (A == &X86::GR64RegClass)
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return &X86::GR64RegClass;
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else if (A == &X86::GR32RegClass)
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return &X86::GR32RegClass;
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else if (A == &X86::GR16RegClass)
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return &X86::GR16RegClass;
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if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
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return A;
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} else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass)
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass)
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass)
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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} else if (B == &X86::GR8_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_NOREXRegClass;
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else if (A == &X86::GR16_ABCDRegClass)
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return &X86::GR16_ABCDRegClass;
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}
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break;
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case 2:
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// 8-bit hi
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if (B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass)
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass)
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass)
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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}
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break;
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case 3:
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// 16-bit
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if (B == &X86::GR16RegClass) {
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if (A == &X86::GR64RegClass)
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return &X86::GR64RegClass;
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else if (A == &X86::GR32RegClass)
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return &X86::GR32RegClass;
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if (A->getSize() == 4 || A->getSize() == 8)
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return A;
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} else if (B == &X86::GR16_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass)
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass)
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass)
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return &X86::GR32_ABCDRegClass;
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} else if (B == &X86::GR16_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass)
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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}
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break;
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case 4:
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// 32-bit
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if (B == &X86::GR32RegClass) {
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if (A == &X86::GR64RegClass)
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return &X86::GR64RegClass;
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if (A->getSize() == 8)
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return A;
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} else if (B == &X86::GR32_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass)
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_ABCDRegClass;
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} else if (B == &X86::GR32_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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}
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break;
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}
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33
test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
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33
test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
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@ -0,0 +1,33 @@
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; RUN: llvm-as < %s | llc -mtriple=thumbv6-elf | not grep "subs sp"
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; PR4567
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define arm_apcscc i8* @__gets_chk(i8* %s, i32 %slen) nounwind {
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entry:
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br i1 undef, label %bb, label %bb1
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bb: ; preds = %entry
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ret i8* undef
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bb1: ; preds = %entry
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br i1 undef, label %bb3, label %bb2
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bb2: ; preds = %bb1
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%0 = alloca i8, i32 undef, align 4 ; <i8*> [#uses=0]
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br label %bb4
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bb3: ; preds = %bb1
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%1 = malloc i8, i32 undef ; <i8*> [#uses=0]
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br label %bb4
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bb4: ; preds = %bb3, %bb2
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br i1 undef, label %bb5, label %bb6
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bb5: ; preds = %bb4
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%2 = call arm_apcscc i8* @gets(i8* %s) nounwind ; <i8*> [#uses=1]
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ret i8* %2
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bb6: ; preds = %bb4
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unreachable
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}
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declare arm_apcscc i8* @gets(i8*) nounwind
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165
test/CodeGen/X86/2009-07-20-CoalescerBug.ll
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165
test/CodeGen/X86/2009-07-20-CoalescerBug.ll
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@ -0,0 +1,165 @@
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; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10
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; PR4587
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; rdar://7072590
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%struct.re_pattern_buffer = type <{ i8*, i64, i64, i64, i8*, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8 }>
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define fastcc i32 @regex_compile(i8* %pattern, i64 %size, i64 %syntax, %struct.re_pattern_buffer* nocapture %bufp) nounwind ssp {
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entry:
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br i1 undef, label %return, label %if.end
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if.end: ; preds = %entry
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%tmp35 = getelementptr %struct.re_pattern_buffer* %bufp, i64 0, i32 3 ; <i64*> [#uses=1]
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store i64 %syntax, i64* %tmp35
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store i32 undef, i32* undef
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br i1 undef, label %if.then66, label %if.end102
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if.then66: ; preds = %if.end
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br i1 false, label %if.else, label %if.then70
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if.then70: ; preds = %if.then66
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%call74 = call i8* @xrealloc(i8* undef, i64 32) nounwind ssp ; <i8*> [#uses=0]
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unreachable
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if.else: ; preds = %if.then66
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br i1 false, label %do.body86, label %if.end99
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do.body86: ; preds = %if.else
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br i1 false, label %do.end, label %if.then90
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if.then90: ; preds = %do.body86
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unreachable
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do.end: ; preds = %do.body86
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ret i32 12
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if.end99: ; preds = %if.else
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br label %if.end102
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if.end102: ; preds = %if.end99, %if.end
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br label %while.body
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while.body: ; preds = %if.end1126, %sw.bb532, %while.body, %if.end102
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%laststart.2 = phi i8* [ null, %if.end102 ], [ %laststart.7.ph, %if.end1126 ], [ %laststart.2, %sw.bb532 ], [ %laststart.2, %while.body ] ; <i8*> [#uses=6]
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%b.1 = phi i8* [ undef, %if.end102 ], [ %ctg29688, %if.end1126 ], [ %b.1, %sw.bb532 ], [ %b.1, %while.body ] ; <i8*> [#uses=5]
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br i1 undef, label %while.body, label %if.end127
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if.end127: ; preds = %while.body
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switch i32 undef, label %sw.bb532 [
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i32 123, label %handle_interval
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i32 92, label %do.body3527
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]
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sw.bb532: ; preds = %if.end127
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br i1 undef, label %while.body, label %if.end808
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if.end808: ; preds = %sw.bb532
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br i1 undef, label %while.cond1267.preheader, label %if.then811
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while.cond1267.preheader: ; preds = %if.end808
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br i1 false, label %return, label %if.end1294
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if.then811: ; preds = %if.end808
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%call817 = call fastcc i8* @skip_one_char(i8* %laststart.2) ssp ; <i8*> [#uses=0]
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br i1 undef, label %cond.end834, label %lor.lhs.false827
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lor.lhs.false827: ; preds = %if.then811
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br label %cond.end834
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cond.end834: ; preds = %lor.lhs.false827, %if.then811
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br i1 undef, label %land.lhs.true838, label %while.cond979.preheader
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land.lhs.true838: ; preds = %cond.end834
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br i1 undef, label %if.then842, label %while.cond979.preheader
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if.then842: ; preds = %land.lhs.true838
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%conv851 = trunc i64 undef to i32 ; <i32> [#uses=1]
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br label %while.cond979.preheader
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while.cond979.preheader: ; preds = %if.then842, %land.lhs.true838, %cond.end834
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%startoffset.0.ph = phi i32 [ 0, %cond.end834 ], [ 0, %land.lhs.true838 ], [ %conv851, %if.then842 ] ; <i32> [#uses=2]
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%laststart.7.ph = phi i8* [ %laststart.2, %cond.end834 ], [ %laststart.2, %land.lhs.true838 ], [ %laststart.2, %if.then842 ] ; <i8*> [#uses=3]
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%b.4.ph = phi i8* [ %b.1, %cond.end834 ], [ %b.1, %land.lhs.true838 ], [ %b.1, %if.then842 ] ; <i8*> [#uses=3]
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%ctg29688 = getelementptr i8* %b.4.ph, i64 6 ; <i8*> [#uses=1]
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br label %while.cond979
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while.cond979: ; preds = %if.end1006, %while.cond979.preheader
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%cmp991 = icmp ugt i64 undef, 0 ; <i1> [#uses=1]
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br i1 %cmp991, label %do.body994, label %while.end1088
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do.body994: ; preds = %while.cond979
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br i1 undef, label %return, label %if.end1006
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if.end1006: ; preds = %do.body994
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%cmp1014 = icmp ugt i64 undef, 32768 ; <i1> [#uses=1]
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%storemerge10953 = select i1 %cmp1014, i64 32768, i64 undef ; <i64> [#uses=1]
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store i64 %storemerge10953, i64* undef
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br i1 false, label %return, label %while.cond979
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while.end1088: ; preds = %while.cond979
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br i1 undef, label %if.then1091, label %if.else1101
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if.then1091: ; preds = %while.end1088
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store i8 undef, i8* undef
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%idx.ext1132.pre = zext i32 %startoffset.0.ph to i64 ; <i64> [#uses=1]
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%add.ptr1133.pre = getelementptr i8* %laststart.7.ph, i64 %idx.ext1132.pre ; <i8*> [#uses=1]
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%sub.ptr.lhs.cast1135.pre = ptrtoint i8* %add.ptr1133.pre to i64 ; <i64> [#uses=1]
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br label %if.end1126
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if.else1101: ; preds = %while.end1088
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%cond1109 = select i1 undef, i32 18, i32 14 ; <i32> [#uses=1]
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%idx.ext1112 = zext i32 %startoffset.0.ph to i64 ; <i64> [#uses=1]
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%add.ptr1113 = getelementptr i8* %laststart.7.ph, i64 %idx.ext1112 ; <i8*> [#uses=2]
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%sub.ptr.rhs.cast1121 = ptrtoint i8* %add.ptr1113 to i64 ; <i64> [#uses=1]
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call fastcc void @insert_op1(i32 %cond1109, i8* %add.ptr1113, i32 undef, i8* %b.4.ph) ssp
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br label %if.end1126
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if.end1126: ; preds = %if.else1101, %if.then1091
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%sub.ptr.lhs.cast1135.pre-phi = phi i64 [ %sub.ptr.rhs.cast1121, %if.else1101 ], [ %sub.ptr.lhs.cast1135.pre, %if.then1091 ] ; <i64> [#uses=1]
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%add.ptr1128 = getelementptr i8* %b.4.ph, i64 3 ; <i8*> [#uses=1]
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%sub.ptr.rhs.cast1136 = ptrtoint i8* %add.ptr1128 to i64 ; <i64> [#uses=1]
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%sub.ptr.sub1137 = sub i64 %sub.ptr.lhs.cast1135.pre-phi, %sub.ptr.rhs.cast1136 ; <i64> [#uses=1]
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%sub.ptr.sub11378527 = trunc i64 %sub.ptr.sub1137 to i32 ; <i32> [#uses=1]
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%conv1139 = add i32 %sub.ptr.sub11378527, -3 ; <i32> [#uses=1]
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store i8 undef, i8* undef
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%shr10.i8599 = lshr i32 %conv1139, 8 ; <i32> [#uses=1]
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%conv6.i8600 = trunc i32 %shr10.i8599 to i8 ; <i8> [#uses=1]
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store i8 %conv6.i8600, i8* undef
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br label %while.body
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if.end1294: ; preds = %while.cond1267.preheader
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ret i32 12
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do.body3527: ; preds = %if.end127
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br i1 undef, label %do.end3536, label %if.then3531
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if.then3531: ; preds = %do.body3527
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unreachable
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do.end3536: ; preds = %do.body3527
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ret i32 5
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handle_interval: ; preds = %if.end127
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br i1 undef, label %do.body4547, label %cond.false4583
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do.body4547: ; preds = %handle_interval
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br i1 undef, label %do.end4556, label %if.then4551
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|
||||
if.then4551: ; preds = %do.body4547
|
||||
unreachable
|
||||
|
||||
do.end4556: ; preds = %do.body4547
|
||||
ret i32 9
|
||||
|
||||
cond.false4583: ; preds = %handle_interval
|
||||
unreachable
|
||||
|
||||
return: ; preds = %if.end1006, %do.body994, %while.cond1267.preheader, %entry
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i8* @xrealloc(i8*, i64) ssp
|
||||
|
||||
declare fastcc i8* @skip_one_char(i8*) nounwind readonly ssp
|
||||
|
||||
declare fastcc void @insert_op1(i32, i8*, i32, i8*) nounwind ssp
|
Loading…
Reference in New Issue
Block a user