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AArch64/ARM64: add non-scalar lowering for more FCVT operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206591 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1313,10 +1313,16 @@ static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
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if (VT.getSizeInBits() == InVT.getSizeInBits())
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if (VT.getSizeInBits() == InVT.getSizeInBits())
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return Op;
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return Op;
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if (InVT == MVT::v2f64) {
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if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
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SDLoc dl(Op);
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SDLoc dl(Op);
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SDValue Cv = DAG.getNode(Op.getOpcode(), dl, MVT::v2i64, Op.getOperand(0));
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SDValue Cv =
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DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
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Op.getOperand(0));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
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} else if (InVT == MVT::v2f32) {
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SDLoc dl(Op);
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SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
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return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
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}
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}
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// Type changing conversions are illegal.
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// Type changing conversions are illegal.
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@@ -316,6 +316,10 @@ unsigned ARM64TTI::getCastInstrCost(unsigned Opcode, Type *Dst,
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 4 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 4 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 },
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 4 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 4 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 4 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 4 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 4 },
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};
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};
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1901
test/CodeGen/ARM64/aarch64-neon-misc.ll
Normal file
1901
test/CodeGen/ARM64/aarch64-neon-misc.ll
Normal file
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