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https://github.com/c64scene-ar/llvm-6502.git
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Provide Thumb2 encodings for basic loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
1e0eab122b
commit
75579f739f
@ -177,6 +177,12 @@ namespace {
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const { return 0; }
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unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
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@ -127,6 +127,7 @@ def imm0_255_not : PatLeaf<(i32 imm), [{
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def t2addrmode_imm12 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
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let PrintMethod = "printAddrModeImm12Operand";
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string EncoderMethod = "getT2AddrModeImm12OpValue";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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@ -134,6 +135,7 @@ def t2addrmode_imm12 : Operand<i32>,
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def t2addrmode_imm8 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
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let PrintMethod = "printT2AddrModeImm8Operand";
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string EncoderMethod = "getT2AddrModeImm8OpValue";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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@ -157,6 +159,7 @@ def t2am_imm8s4_offset : Operand<i32> {
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def t2addrmode_so_reg : Operand<i32>,
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ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
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let PrintMethod = "printT2AddrModeSoRegOperand";
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string EncoderMethod = "getT2AddrModeSORegOpValue";
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let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
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}
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@ -823,19 +826,26 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
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multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
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def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), iii,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
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def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
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opc, ".w\t$Rt, $addr",
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[(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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let Inst{23} = 1;
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let Inst{22-21} = opcod;
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let Inst{20} = 1; // load
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bits<4> Rt;
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let Inst{15-12} = Rt{3-0};
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bits<16> addr;
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let Inst{19-16} = addr{15-12}; // Rn
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let Inst{11-0} = addr{11-0}; // imm
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}
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def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), iii,
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opc, "\t$dst, $addr",
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[(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
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def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
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opc, "\t$Rt, $addr",
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[(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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@ -846,10 +856,18 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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// Offset: index==TRUE, wback==FALSE
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let Inst{10} = 1; // The P bit.
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let Inst{8} = 0; // The W bit.
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bits<4> Rt;
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let Inst{15-12} = Rt{3-0};
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bits<13> addr;
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{9} = addr{8}; // U
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let Inst{7-0} = addr{7-0}; // imm
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}
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def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
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def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$Rt, $addr",
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[(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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@ -857,12 +875,20 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{22-21} = opcod;
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let Inst{20} = 1; // load
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let Inst{11-6} = 0b000000;
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bits<4> Rt;
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let Inst{15-12} = Rt{3-0};
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bits<10> addr;
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let Inst{19-16} = addr{9-6}; // Rn
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let Inst{3-0} = addr{5-2}; // Rm
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let Inst{5-4} = addr{1-0}; // imm
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}
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// FIXME: Is the pci variant actually needed?
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def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), iii,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
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def pci : T2Ipc <(outs GPR:$Rt), (ins i32imm:$addr), iii,
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opc, ".w\t$Rt, $addr",
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[(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
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let isReMaterializable = 1;
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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@ -871,23 +897,35 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{22-21} = opcod;
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let Inst{20} = 1; // load
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let Inst{19-16} = 0b1111; // Rn
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bits<4> Rt;
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bits<12> addr;
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let Inst{15-12} = Rt{3-0};
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let Inst{11-0} = addr{11-0};
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}
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}
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/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
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multiclass T2I_st<bits<2> opcod, string opc,
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InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
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def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), iii,
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opc, ".w\t$src, $addr",
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[(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
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def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
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opc, ".w\t$Rt, $addr",
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[(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0001;
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let Inst{22-21} = opcod;
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let Inst{20} = 0; // !load
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bits<4> Rt;
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let Inst{19-16} = Rt{3-0};
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bits<16> addr;
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let Inst{19-16} = addr{15-12}; // Rn
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let Inst{11-0} = addr{11-0}; // imm
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}
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def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), iii,
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opc, "\t$src, $addr",
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[(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
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def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
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opc, "\t$Rt, $addr",
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[(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0000;
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let Inst{22-21} = opcod;
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@ -896,15 +934,31 @@ multiclass T2I_st<bits<2> opcod, string opc,
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// Offset: index==TRUE, wback==FALSE
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let Inst{10} = 1; // The P bit.
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let Inst{8} = 0; // The W bit.
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bits<4> Rt;
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let Inst{19-16} = Rt{3-0};
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bits<13> addr;
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{9} = addr{8}; // U
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let Inst{7-0} = addr{7-0}; // imm
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}
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def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$src, $addr",
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[(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
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def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$Rt, $addr",
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[(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0000;
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let Inst{22-21} = opcod;
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let Inst{20} = 0; // !load
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let Inst{11-6} = 0b000000;
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bits<4> Rt;
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let Inst{15-12} = Rt{3-0};
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bits<10> addr;
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let Inst{19-16} = addr{9-6}; // Rn
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let Inst{3-0} = addr{5-2}; // Rm
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let Inst{5-4} = addr{1-0}; // imm
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}
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}
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@ -173,6 +173,13 @@ public:
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return Encoded;
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}
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unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getSORegOpValue - Return an encoded so_reg shifted register value.
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unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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@ -632,6 +639,54 @@ getSORegOpValue(const MCInst &MI, unsigned OpIdx,
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return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
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}
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unsigned ARMMCCodeEmitter::
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getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO1 = MI.getOperand(OpNum);
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const MCOperand &MO2 = MI.getOperand(OpNum+1);
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const MCOperand &MO3 = MI.getOperand(OpNum+2);
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// Encoded as [Rn, Rm, imm].
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// FIXME: Needs fixup support.
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unsigned Value = getARMRegisterNumbering(MO1.getReg());
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Value <<= 4;
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Value |= getARMRegisterNumbering(MO2.getReg());
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Value <<= 2;
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Value |= MO3.getImm();
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return Value;
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}
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unsigned ARMMCCodeEmitter::
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getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO1 = MI.getOperand(OpNum);
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const MCOperand &MO2 = MI.getOperand(OpNum+1);
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// FIXME: Needs fixup support.
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unsigned Value = getARMRegisterNumbering(MO1.getReg());
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// Even though the immediate is 8 bits long, we need 9 bits in order
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// to represent the (inverse of the) sign bit.
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Value <<= 9;
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Value |= ((int32_t)MO2.getImm()) & 511;
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Value ^= 256; // Invert the sign bit.
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return Value;
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}
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unsigned ARMMCCodeEmitter::
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getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO1 = MI.getOperand(OpNum);
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const MCOperand &MO2 = MI.getOperand(OpNum+1);
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// FIXME: Needs fixup support.
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unsigned Value = getARMRegisterNumbering(MO1.getReg());
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Value <<= 12;
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Value |= MO2.getImm() & 4095;
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return Value;
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}
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unsigned ARMMCCodeEmitter::
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getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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@ -101,4 +101,17 @@
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@ CHECK: dmb ish @ encoding: [0x5b,0x8f,0xbf,0xf3]
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dmb ish
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@ CHECK: str.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0xc1,0xf8]
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str.w r0, [r1, #4092]
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@ CHECK: str r0, [r1, #-128] @ encoding: [0x80,0x0c,0x41,0xf8]
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str r0, [r1, #-128]
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@ CHECK: str.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x41,0xf8
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str.w r0, [r1, r2, lsl #2]
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@ CHECK: ldr.w r0, [r0, #4092] @ encoding: [0xfc,0x0f,0xd0,0xf8]
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ldr.w r0, [r0, #4092]
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@ CHECK: ldr r0, [r0, #-128] @ encoding: [0x80,0x0c,0x50,0xf8]
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ldr r0, [r0, #-128]
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@ CHECK: ldr.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x50,0xf8]
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ldr.w r0, [r0, r1, lsl #2]
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